Abstract: A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate.