Abstract: An integrated circuit having an option between two or more configurations and also using a patterned ion-implant for impressing data (such as a ROM section of the circuit) may advantageously perform the option-specification simultaneously with the ROM; using a powerless option-specifying circuit permits testing portions of the circuit before the implantation step.

Abstract: An integrated circuit chip includes a top layer of dielectric penetrated by conductive vias connecting electrical contacts within the integrated circuit proper to a network of electrical leads disposed on top of the dielectric layer; the network of leads, in turn, being connected to an array of contact pads adapted for simultaneous solder connection to a leadframe.

Abstract: A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to produce a voltage pattern that has one high node and one low node (72, 74) for a normal cell and two intermediate voltage nodes for a shorted cell. A following logic circuit (76) responds to the voltage pattern to produce an output voltage that has one value when the cell is functioning correctly and another value when the cell is shorted.

Abstract: An address (n) is associated with a sort element (30) so that input signals are compared with each other, or with the address (n) in the case of a null input (N). Several elements (30) are interconnected to provide unique signal routing from any input to a particular output, depending upon a characteristic of an input signal itself without reference to other input signals.

Abstract: A method of making a trench capacitor employs an N-type switchable plate formed in a P-type substrate for holding charge at either zero volts or a positive TC voltage and a P-type ground plate that fills in a trench around a memory cell, so that P-type dopant diffuses through a thin oxide insulator to form a channel stop and a pinhold short through the oxide is self-healing by the formation of a reverse-biased P-N diode that cuts off the flow of current through the pinhole.

Abstract: A buffer circuit accepting TTL input levels and generating logic-level signals incorporates means to reduce the power consumption in the circuit in the active phase as well as the inactive phase, without imposing additional restrictions on the user.

Abstract: A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the gate to source voltage of the detector transistor (36) equal to the approximate threshold voltage of the transistor. The drain of the detector transistor (36) gates an amplifier transistor (30) which inhibits or passes a read signal (18) to the gate of a digit line pull down transistor (32) which provides an active pull down on a digit line (26) that is precharged to a high voltage prior to a memory read cycle.

Abstract: A ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR between two adjacent column select signals with no more than three transistors and effective for generation of a sinking current to maximize the slew rate of the output signal nodes.

Abstract: Transistors (10) having lateral gaps between their source and drain and the gate are interconnected in a ROM to receive program code.In one embodiment of the invention (FIG. 3), the gaps of selected transistors (42) are subjected to a phosphorous implant (44) to create lightly doped n.sup.- regions (26,28) connecting the source (18) and drain (20) to the gate (14), and function normally. The other transistors (40) do not receive the phosphorous implant, and thus have a higher threshold voltage.In another embodiment of the invention (FIG. 2) all of the transistors receive the phosphorous implant to create the n.sup.- regions (26,28) connecting the source and drain to the gate, and the n.sup.- regions of selected transistors (32) are counter-doped with a boron implant (34) so as to raise their threshold voltages, while the other transistors (30) are not counter-doped and function normally.In both embodiments, programming can occur late in the processing of the ROM.

Abstract: A multiple input differential sense amplifier including a pair of signal inputs and comprising a bank of n-channel MOS transistors for receiving said multiple inputs for connection to one of said signal inputs. The other of said signal inputs can be provided with a fixed bias input, or a complementary input from a complementary bank of n-channel MOS transistors.

Abstract: An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome word points to errors in the data only, not to errors in the parity bits. One of the data addresses in the field is reserved as a no-error flag and a Kth parity check bit associated with the syndrome word flags an error in the parity bits.