Abstract: When film is transmitted by television, the same frame of film is used to generate both interlace television fields. This results in the information carried by the second field being temporally displaced from the original by 20 ms. This displacement gives rise to judder and double image artifacts in the received image. To overcome these defects the intermediate fields are generated from the original film frames by double sided motion compensated interpolation wherein the motion information is calculated using double sided block matching. The invention may be applied either in a television receiver or video signal decoder or in the television studio before the television signal is transmitted.

Abstract: The invention discloses a method for coding a video image on a pixel block basis in a transmission system including at least one transmitter and one receiver, where the video image is in one of several possible display formats. The method comprises:(a) defining a first image display format that encompasses each of the several image display formats;(b) dividing the first image format into pixel blocks;(c) assigning labels to the first image format blocks so that they can be individually addressed;(d) selecting a second image display format for the video image that is encompassed by the first image display format; and(e) coding the video image with reference to the individual addresses of the first image format block.A method of decoding transmissions coded by the disclosed coding method is also presented.The invention is applicable to videophones and television transmission systems.

Abstract: A liquid crystal display includes pixels that are arranged in columns and rows. Data line drivers responsive to a video signal develop output signals in data lines that correspond with the columns, respectively. An adjustment data line driver is provided. The adjustment data line driver is responsive to a reference DC constant signal at a mid-range of the video signal. An output signal of the adjustment data line driver is coupled to the other data line drivers in a negative feedback manner to compensate for output signal variations in the other data line drivers.

Abstract: An auxiliary video data slicer for extracting auxiliary video information from a video signal includes a peak detector. The peak detector determines a peak amplitude of horizontal sync pulses that are included in the video signal and a peak amplitude of a run-in-clock (RIC) waveform that is included in an auxiliary information component of the video signal. A variable threshold level for the peak detector is varied in a first range to detect the peak amplitude of the sync pulses. A threshold voltage for detecting the leading edge of sync pulses is derived from the peak amplitude of the sync pulses. The location of the RIC waveform within a video line interval is determined in response to detection of a sync pulse edge. The variable threshold level of the peak detector is varied in a second range to detect the peak amplitude of the RIC signal. A data slicing threshold level for extracting auxiliary video information is derived from the peak value of the RIC signal.

Abstract: Motion compensated video output signal (SO) produced by a soft switching or "fading" (SSW) between the a motion compensated interpolation (MCI) and a "fallback" mode (FFI) (e.g., intra-field), controlled by a "measure of confidence" (CF) in the reliability of the estimated motion vector. The confidence measure includes the following two components, namely: (i) a "basic confidence measure" (e.g., a block based, minimum motion estimation error (BME) and (ii) a measure based on the motion velocity or "speed" of movement of the motion vector or its horizontal (MVX) and vertical components (MVY).

Abstract: A method for signal equalization/ghost cancellation with an equalizing filter includes synthesizing a first equalizing filter function (LMS 1) with N (an integer) taps and associated coefficients. The respective coefficients are adjusted to minimize the error between a received reference signal output by the synthesized equalizing filter function and a non-distorted reference signal. The adjusted coefficients are evaluated to determine P (an integer) groups of M (an integer) taps and associated coefficients which contribute to said synthesized equalizing filter function according to a predetermined criterion and wherein P times M is less than N. A second equalizing filter function is synthesized corresponding to the first equalizing filter function with coefficients other than the P groups of M coefficients set to zero, and the P groups to M coefficients are adjusted to minimize the error.

Abstract: A first input-first output type circuit manages m n-bit words using m stages connected in series with first and second non-overlapping clock signals controlling even-numbered and odd numbered ones of the m stages, respectively. A process for controlling the circuit involves a first write step during which each word in a first half of the m words is written into both an odd-numbered stage and a successive even numbered stage so that m/2 of the m words occupy all m of the stages. After the first write step is completed, a second write step begins during which the m/2 words written during the first write step are shifted and stored in the ((m/2)+1)-th through m-th stages. Writing is disabled in each of the m stages beginning with the m-th stage and proceeding successively to the first stage. The m/2 words not written during the first write step are written into those stages not yet disabled in the same manner as in the first write step.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A third transistor responsive to an output signal of a stage downstream of the given stage applies a control signal to a gate electrode of the pull-down transistor to render the pull-down transistor conductive.

Abstract: A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which consist of a PMOS and an NMOS transistor. The source of the PMOS transistor is connected with the drain of the NMOS transistor and the drain of the PMOS transistor is connected with the source of the NMOS transistor. The gate of the PMOS transistor receives inverted signals with respect to the gate of the NMOS transistor. Two partial output sum signals are generated by two of the switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of the adder is available at the output of the inverter.

Abstract: A level translator includes a latch, a pair of transistors responsive to a switching input voltage and operating in a complementary manner and a pair of zener diodes operating as level shifters. The Zener diodes are coupled between the pair of transistors and the latch. An output transistor is coupled to the latch and produces an output voltage that is level translated with respect to the input voltage. A second embodiment of the invention includes a level translator that produces a first voltage at selectively one of first and second levels and a second voltage at selectively one of third and fourth levels. The first, second, third and fourth levels are different from each other such that in total four different levels are produced. The first and second voltages are coupled to control gates of a pair of transistors operating as a transmission gate.

Abstract: A television receiver has a switched mode power supply controller, which may be deflection synchronized, which produces pulses in a power transformer. To power the controller during startup, before the internal power supply has started, a storage capacitor on the power supply input of the controller is coupled through a current limiting resistance to a rectified voltage from the AC mains so as to charge the storage capacitor during first polarity phases of the AC mains. The current limiting resistance includes a positive temperature coefficient (PTC) element which increases its impedance as it heats, to reduce power dissipation after initial connection of the television receiver to AC mains. In addition, a diode is coupled in a current path to the storage capacitor to charge the capacitor to the same polarity as during opposite polarity phases of the AC mains.

Abstract: For improving motion portrayal and reducing undesirable artifacts, e.g., double images and "mouse teeth" structure, each pixel of intermediate fields in a field rate up-conversion system is determined from nearby pixels in the existing fields using an adaptive linear filtering method (or apparatus) which provides: calculation of sums of differences (one or more for each pixel involved in the adaptive filter); calculation of basic coefficients (one for each pixel involved in the adaptive filter); one-dimensional median filtering of the coefficients; two-dimensional linear filtering of coefficients; normalization of coefficients; calculation of main interpolated pixel values; and correction of interpolation in the case of fast motion.

Abstract: The present invention relates to a method, identification device and verification device for identification and/or performing digital signature which allows zero-knowledge access control. For many applications, e.g. smart cards for Pay-TV purposes, credit cards, passports, dongels or other kind of electronic keys, unforgeable systems for access control or digital signature are required. Such access control and signature systems may include public keys. But in many of such public key systems the key management becomes very complicated when the number of users increases. The invention uses the fact that it is difficult to compute roots mod n when factoring of n is unknown. The invention is based on the identity: x.sup.d (x.sup.-1).sup.d =1 mod n which is computed and verified between an identification device and a verification device. An authority records seed data, the modulus n, a pseudo-random function and a set of numbers derived from roots modulo n on an identifier device.

Abstract: In a television receiver, a microprocessor controls a horizontal deflection circuit which is coupled to run mode power supply to define a standby operating mode and a run operating mode. The microprocessor has a power-up reset input terminal which initializes operation upon application of AC mains power. The run mode power supply is coupled to at least one load which is subject to overcurrent or overvoltage faults. A fault detection circuit detects fault conditions in the run mode power supply loads such as overvoltage or overcurrent and anomalous vertical deflection current. Upon fault detection the fault detection circuit triggers a power up reset circuit which applies a momentary reset pulse to the power-up reset input of the microprocessor. Upon receipt of the reset pulse, the microprocessor controls the horizontal deflection circuit to place the run mode power supply in the standby operating mode.

Abstract: A video signal is applied to a kinescope having scan velocity modulation for improving picture sharpness in the vertical direction. Pictures from video signals of a type having non-interpolated and vertically interpolated lines (e.g., interlace-progressive up-converted) will tend to exhibit a significant reduction of sharpness in vertical direction. This problem is corrected by applying scan velocity modulation only to the interpolated lines of the video signal. Furthermore, the vertical deflection is restricted to horizontal structures or real vertical transitions, respectively. In order to have a high noise immunity of this sensitive processing, the resulting luminance amplitude of the shifted line as well as the vertical deflection is controlled to be strongly dependent on the current video signal (soft decision).

Abstract: A noisy input signal x is filtered with a restoration filter of median type to generate a filtered input signal y. The sum of the absolute differences between filtered and unfiltered signal is calculated for each position of a sliding window within the input signal representing a local estimate of the noise, and is combined with a global measure of the input signal noise to compute two coefficients a and b which are respectively applied to the unfiltered and filtered signal to generate the output signal z=a*x+b*y which is both globally and locally adapted to the structure of displayed images. Advantageously different kinds of filters operate in parallel, whereby the kind of filter elected is locally adapted to the picture activity.

Abstract: For progressive scan conversion adjacent fields cannot be used to interpolate moving objects because motion blur will be introduced then. The most simple solution is to insert the average of the two adjacent lines for each missing line. A technique superior to vertical averaging represents the DIAG3 algorithm, where according to the found minimum gradient the orientation of the interpolation filter is chosen. But in case of high diagonal frequencies interpolation errors will occur. Therefore it is tested if the reconstructed pixel value exceeds or falls below the pixel values in the two adjacent lines of the input signal. If this happens, instead of one of the detected diagonal directions the vertical direction is taken, it.e. a vertical averaging is carried out.

Abstract: An access control system involves a first cryptographic device communicating with a second cryptographic device using a modulo-based protocol. To transmit a message from the first device to the second device, a random number is combined with the number representing the message without using a modulo operation. As a result, the message is hidden. By performing a modulo operation in the second device on the received hidden message, the original message can be recovered. Modular operations by the first device can be avoided reducing the number of modular operations.

Abstract: In a system for controlling access to signals such as pay-TV signals, the signals include data packets that are received and by a decoder and forwarded to a smart card for access authorization processing. The data packets contain information that updates entitlement or access authorization data inside the smart card. Time-related data is added to the data packets. The smart card checks to determine if the time-related data evolves between two successive packets. If not, the smart card inhibits the delivering of descrambling parameters to the decoder.

Abstract: A system providing access control, including encryption and decryption capability, replaces a public key directory by a transmission between an authority, or a sender S, and a receiver R of a "seed" value. The seed is processed to provide both identity information for R and public keys, i.e. a "virtual public key directory", or VPKD. The VPKD is generated prior to execution of the algorithm requiring the public directory, i.e. the host algorithm.