Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.

Abstract: A data line defect avoidance structure for a display device having an array of display elements arranged in rows and columns includes a plurality of repair lines overlapping the ends of data lines which extend between the columns. Each repair line spans a set of data lines, and there is a sufficient number of repair lines to span all the data lines in the array. One end of each repair line can be welded to a data line during fabrication to decrease the number of steps required for avoiding an open in a data line.

Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. The select line scanners are independently operable by the provision separate power supplies and clock generators. During testing, one scanner is made to look like a high impedance to the scanner being tested. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.

Abstract: A protection circuit for a solid state instrument includes a plurality of fuses and a switching device arranged in parallel with the input capacitance of the solid state instrument, The fuses protect the instrument from high voltage surges, and the switching device protects the instrument from lower voltage surges. The fuses and the switching device are solid state devices and thus can be fabricated along with the solid state instrument.

Abstract: A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line of a most significant bit bus by a first capacitive device, the control electrode of every transistor is also coupled to one line of a least significant bit bus by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an enable signal the transistor is turned on and current flows from the input terminal to an output node. Each transistor within the demultiplexer thus acts as a three state gate.

Abstract: A system for applying brightness signals to the pixels of a display device includes a transmission gate for each column of pixels. The control electrodes of the transmission gates are precharged to the threshold voltage of the gates to substantially increase the speed of the system. Comparators compare brightness voltages to a reference ramp voltage to enhance the speed and accuracy of the system.

Abstract: A logic circuit includes pull-up and pull-down transistors and a capacitance, the principal conducting paths of the transistors and the capacitance being coupled in series between a first supply bus and a source of time varying potential. The pull-up transistor is coupled to the capacitance and the capacitance is coupled to the time varying potential. First and second logic signals are applied to the control electrodes of the first and second transistors respectively. The time varying potential is arranged to limit the charge passed by the pull-up transistor permitting use of a relatively small pull-down transistor. The time varying potential has an amplitude sufficiently large to tend to stress the pull-up transistor if such transistor is non conducting. A selectively conductive element (diode) is coupled between a point of clamping potential and the interconnection of the pull-up transistor and capacitance.

Abstract: A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked voltage of a second phase and the control electrode of the other transistor receives an input signal. An inverter is arranged between the node and the output terminal.

Abstract: A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.

Abstract: A circuit for testing a liquid crystal display for open data lines, for identifying select lines shorted to data lines, and for identifying failed data line scanner stages includes thin film transistors arranged between each data line and a segmented bus. A sectioned shift register sequentially actuates the thin film transistors and the bus segments are monitored while data signals are applied to the data lines. The absence of a voltage on the bus indicates an open data line. The bus is also monitored while select signals are applied to the select lines and the shift register sequentially actuates the thin film transistors, the presence of a voltage on the bus indicates a short between a data line and a select line.

Abstract: A variable width pulse generator includes a plurality of logic stages which are coupled cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the width pulse.

Abstract: A variable width pulse generator includes a plurality of logic stages which are coupled in cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the variable width pulse.