Abstract: A device for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, and at least one group of fuses to store the address of a faulty element of the memory. Each fuse is associated with a row/column address pair. Through the blowing of certain fuses in the group after testing of a memory element, the address either of a column element, if the faulty element is a column element, or of a row element, if the faulty element is a row element, is stored. Only the row addresses are enabled when the stored address is that of a row element, and only the column addresses are enabled when the stored address is that of a column element, in order to address either a row redundant element or a column redundant element.

Abstract: A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists:for one battery, in associating said battery with a row/column address pair;in memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a column element or that of a row element if the faulty element is a row element;and in enabling only the row addresses when the stored address is that of a row element or only the column addresses when the stored address is that of a column element, to address either a row redundant element or a column redundant element.

Abstract: An ultra-fast sample-and-hold circuit for the processing of analog signals comprises a diodes bridge: an input signal VE is applied to the input point and copied at the output point; the output signal is memorized in a capacitance. At the midpoints of the bridge, two current sources are applied. The voltages at the midpoints are servo-linked, in the hold mode, to the output voltage by means of a voltage follower and diodes mounted diagonally across the bridge, the two switches of the current sources being controlled by a signal clock signal. It is applied to signal processing chains in instrumentation, radar and telecommunications.

Abstract: The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructions sets, the sequencer having a line and column architecture and very widely produced in the form of a transistor and capacitor matrix, functioning with decoding transistors, preload transistors and a matrix for defining the phases of operating cycles.

Abstract: The invention pertains to the programming of electrically programmable read-only memories (EPROM, EEPROM) made in the form of integrated circuits. To optimize the data programming process, two stages are planned: the first stage is a conventional but short programming stage, designed to memorize data during a relatively short period of time. In the second stage, is a longer repeat programming stage performed in a way which is internal to the integrated circuit, i.e. the data is read in the memory and re-recorded at the same places without its being necssary to apply this data again to the inputs of the integrated circuits.

Abstract: An electrically programmable non-volatile memory includes a matrix of memory cells accessible by rows and columns, write and read circuits which apply potentials, representing the programmed datum or representing the read command, to the rows and columns. The memory also includes a device which controls the interconnection of the write and read circuits with the memory cells, wherein N memory cells are programmed simultaneously, N being greater than 1, each memory cell setting up a current surge when it is programmed at "1". The memory also includes a device for deactivating, one by one, the write circuits corresponding to the N memory cells where there is a change-over from a programming mode to a read mode, and a structure to short-circuit the deactivation device at the change-over to the programming mode.

Abstract: The invention concerns an instructions sequencer for a microprocessor, the sequencer comprising an instructions decoding unit followed by a unit for determining the steps which defines the cycle instants at which must be activated the different function controls issuing from the sequencer, this step determination unit being produced in a particularly simple manner with a matrix of transistors in lines and columns, the transistors of one line being in series and the transistors of a column all being controlled by the same clock step, among the transistors, certain (T1) are depleted and are thus conductive whatever the clock step, while others are enriched and are only conductive during the step corresponding to their column.

Abstract: A method of manufacturing a DMOS is disclosed. On a polysilicon gate layer, a multiple dielectric mask including studs (71) defines a window (70) for body implantation (80) into a substrate. Unmasked regions of polysilicon and substrate are oxidized to form oxide regions (84,85,88). Subsequent to the removal of the protective studs and a portion of the oxide, remaining oxide regions (90,91,92) act as a mask for source implantation (99,100).

Abstract: The present invention pertains to a dynamic memory. The voltage of the hot spot of the storage capacitor is carried to a value such that all the cells comprise the same logic value, owing to a potential generator. It is thus possible to write and read bit fields on a large-capacity memory at high speed. This device has applications with respect to image memories and for manufacturing tests.

Abstract: An integrated circuit of the logic circuit type includes a matrix of memory cells of the floating-gate transistor type, write and read circuits and circuitry to handle the interconnection of these circuits with the memory. The integrated circuit receives a general supply voltage Vcc, a programming voltage Vpp and an external clock signal divided into two complementary clock signals. The clock signals acts on, among others, the functioning of the write circuits. The integrated circuit further includes a circuit to detect the presence of internal clock signals. The circuit sends a signal prohibiting write operations in the memory when it detects the absence of one of the internal clock signals.

Abstract: A voltage switch-over circuit, depending on a switch-over signal, delivers either a first voltage Vpp or a second voltage Vcc at its output, the voltage Vpp being greater than the voltage Vcc. The said circuit consists of a first MOS transistor with one of its electrodes connected to the voltage Vcc and a set of two series-connected MOS transistors with one of their electrodes connected to the voltage Vpp and with their two gates connected together so as to create a floating node at the common point between the two MOS transistors, the other electrode of the first MOS transistor and the other electrode of the set of two MOS transistors being connected together, and the gates of the first MOS transistor and those of the set of two MOS transistors respectively receiving the switch-over signal and the reverse switch-over signal.

Abstract: The invention provides a frequency-voltage converter having a voltage source; a first capacitor, a second capacitor, a current generator and a sequencer receiving a recurrent signal; said first capacitor being charged to a value Vo after a time To, then discharged by a discharge current Jd proportional to the square of the instantaneous residual voltage in said first capacitor, during a time T-To; the residual charge which is present in the first capacitor after the time T being recopied at the beginning of each recurrence into said second capacitor.

Abstract: An analog digital converter is used to convert differential analog voltages, namely voltages with reference potentials that are not at ground. The arrangement described requires only one differential amplifier.

Abstract: A circuit is disclosed for the transmission of digital signals on a bifilary line, especially a telephone line. The circuit disclosed is a so-called S interface circuit which has to produce digital signals within certain set limits. The proposed circuit uses four differential amplifiers, each controlling an output transistor (N-channel MOS transistors and P-channel MOS transistors). The amplifiers receive feedback to maintain the overvoltages within acceptable limits. The invention applies especially to the setting up of integrated service digital telephone networks.