Abstract: An architecture for a multi-stage manycore processor shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

Abstract: The invention enables dynamic, software application load adaptive optimization of data processing capacity allocation on a shared processing hardware among a set of application software programs sharing said hardware. The invented techniques allow multiple application software programs to execute in parallel on a shared CPU, with application ready-to-execute status adaptive scheduling of CPU cycles and context switching between applications done in hardware logic, without a need for system software involvement. The invented data processing system hardware dynamically optimizes allocation of its processing timeslots among a number of concurrently running processing software applications, in a manner adaptive to realtime processing loads of the applications, without using the CPU capacity for any non-user overhead tasks.

Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.

Abstract: The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions.

Abstract: The invention provides hardware logic based techniques for a set of processing tasks of a software program to efficiently communicate with each other while running in parallel on an array of processing cores of a multi-core data processing system dynamically shared among a group of software programs. These inter-task communication techniques comprise, by one or more task of the set, writing their inter-task communication information to a memory segment of other tasks of the set at the system memories, as well as reading inter-task communication information from their own segments at the system memories. The invention facilitates efficient inter-task communication on a multi-core fabric, without any of the communications tasks needing to know whether and at which core in the fabric any other task is executing at any given time. The invention thus enables flexibly and efficiently running any task of any program at any core of the fabric.

Abstract: Adaptive data processing systems and methods, comprising functions of preparing a primary input from a preliminary primary input, preparing a secondary input from a preliminary secondary input, and producing an output from the primary and secondary inputs, wherein preparing the secondary input is adaptive to contents of the preliminary primary input that is advanced in timing w.r.t. the primary input. Adaptive data processing techniques thus cause the secondary input to be in same frame phase as the primary input for producing the output, even though the secondary input is formed (in part) based on primary input contents, while such forming of the secondary input consumes multiple clock cycles. Moreover, the techniques enable preparing the primary input from the preliminary primary input while the preliminary primary input is used for preparing the secondary input, which, in turn, is used, along with the primary input, in producing the adaptive data processor output.