Abstract: Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth from the first surface. Spaced apart source and drain regions of the second conductivity type are included in the tub region of second conductivity type at the surface, to define single conductivity junctions of the second conductivity type with the tub region of second conductivity type. The spaced apart source and drain regions extend into the tub region a second depth that is less than the first depth. A trench is included in the tub region, between the spaced apart source and drain regions, and extending from the surface into the tub region to a third depth that is more than the second depth but is less than the first depth. An insulated gate electrode is included in the trench.

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.

Abstract: A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. In order to compensate for the junction with the substrate, the doping density of the substrate region is raised to counteract the shared charge. Furthermore, the proximity of the source and drain regions leads to a potential leakage due to the drain field which can be compensated for by reducing the maximum tub depth compared to a low capacitance Fermi-FET and a contoured-tub Fermi-FET while still satisfying the Fermi-FET criteria. The tub depth is maintained below a maximum tub depth. Short channel effects may also be reduced by providing source and drain extension regions in the substrate, adjacent the source and drain regions and extending towards the channel regions.

Abstract: A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region. The drain pocket implant region acts as a drain field stop to reduce or prevent drain-to-source field reach-through. Reduced low drain field threshold voltage, significantly reduced drain induced barrier lowering and reduced threshold dependence on channel length may be obtained, resulting in higher performance in short channels.

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.

Abstract: A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. The diffusion capacitance is thereby reduced compared to a tub having a uniform tub depth, so that a high saturation current is produced at low voltages. The contoured-tub may be formed by an additional implant into the substrate using the gate as a mask.

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300.ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600.ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively.

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300 .ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600 .ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively.

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Abstract: A random access memory (RAM) includes a plurality of sensing circuits. During a read operation, the RAM detects that one of the sensing circuits has sensed a binary digit. In response, the read operation is terminated and an idle operation is initiated to provide a self-timing RAM. During a write operation, the data which is stored in a RAM cell is also sensed by one of the sensing circuits and the memory detects that one of the sensing circuits has sensed the stored data. In response, the write operation is terminated and an idle operation is initiated. Self-timing read and write operations are thereby provided.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a and additional pull-up circuits to enhance high speed pair of symmetrical transfer function output inverters operation. The outputs of all of the differential latching inverters may be directly connected to a pair of OR gates with the output of one OR gate signifying that a logical ONE has been read and the output of the second OR gate signifying that a logical ZERO has been read. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: The pass transistors in a random access memory array are activated only upon coincident (simultaneous) selection of both the associated row and the associated column of the memory cell; otherwise, activation of the pass transistors is prevented. Thus, when a word line is selected, only the pass transistors in the memory cell corresponding to a simultaneously selected bit line is active, rather than all of the pass transistors pairs connected to the word line. Transient power consumption during word line selection and deselection is thereby reduced. Coincident pass transistor activation may be obtained by providing a column select line for each column of the memory array, and gating means in each cell which electrically activates the associated pass transistors only upon simultaneous selection of the associated column select line and the associated word line, and for preventing activation of the associated pass transistors otherwise.

Abstract: A high current Fermi-FET includes an injector region of the same conductivity type as the Fermi-Tub region and the source and drain regions, located adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate the relatively low doping concentration of the Fermi-Tub and the relatively high doping concentration of the source region. The injector region controls the depth of the carriers injected into the channel and maximizes injection of carriers into the channel at a predetermined depth below the gate. The injector region may also extend to the Fermi-tub depth to decrease bottom leakage current. Alternatively, a bottom leakage current control region may be used to decrease bottom leakage current. Lower pinch-off voltage and increased saturation current are obtained by providing a gate sidewall spacer which extends from adjacent the source injector region to adjacent the sidewall of the polysilicon gate electrode of the Fermi-FET.

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Abstract: An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.

Abstract: A Fermi-FET includes a Fermi-tub region at a semiconductor substrate surface, wherein the Fermi-tub depth is bounded between a maximum tub depth and a minimum tub depth. The Fermi-tub depth is sufficiently deep to completely deplete the Fermi-tub region by the substrate tub junction at the threshold voltage of the field effect transistor, and is also sufficiently shallow to produce a closed inversion injection barrier between the source region and the drain region below the threshold voltage of the Fermi-FET. High saturation current and low leakage current are thereby produced simultaneously. Source and drain injector regions and a gate sidewall spacer may also be provided.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: A data input register for a random access memory includes a data input line which is coupled to TRUE and COMPLEMENT outputs. A first and a second Ring Segment Buffer is connected to a respective one of the TRUE and COMPLEMENT outputs. The Ring Segment Buffer produces TRUE and COMPLEMENT binary signals at relatively fast rise time compared to the relatively slow rise time binary input signal. The Ring Segment Buffer outputs are coupled to a write control circuit for writing data into a selected memory cell of a random access memory array. The data input circuit architecture can also be used to produce relatively fast rise time TRUE and COMPLEMENT binary signals from a relatively slow rise time binary input signal for other applications.