Patents Assigned to Tier Logic
  • Programmable latch based multiplier
    Patent number: 7795913
    Abstract: A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: September 14, 2010
    Assignee: Tier Logic
    Inventor: Nij Dorairaj
  • Three dimensional integrated circuits
    Patent number: 7446563
    Abstract: A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: November 4, 2008
    Assignee: Tier Logic
    Inventor: Raminda Udaya Madurawe