Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.

Abstract: The waveform generator includes a free-running ring oscillator, and algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a rurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: The methods described herein are directed at securing information in storage media such as optical discs, magnetic disks or a combination thereof. In particular the methods describe embedding a first stream of data in a second stream of data by modulating the location of transition edges in the second stream of data. A method for writing data to a storage medium includes the steps of representing the raw (first) data to be written to the storage medium as a sequence of bits in a format appropriate for writing to a storage medium; representing second data (supplemental data) as a second sequence of bits and writing the first sequence of bits to the storage medium as a corresponding sequence of pits along a track, wherein the location of the pits along the track represents the stored first data, and while writing the first sequence of pits, modulating the locations at which transition edges of the sequence of pits are written to embed the second data in the sequence of pits.

Abstract: A method of processing a serial data stream carrying data at a rate established by an underlying clock signal, the method involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time-stamps; and based at least in part on the sequence of time-stamps, recovering the data from the serial data stream.

Abstract: A digital storage medium storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit, the electronic data implementing a library of shim cells, wherein each of the shim cells in the library represents a physical embodiment of a different clock driver cell of a plurality of clock driver cells and wherein all of the shim cells in the library are interchangeable in the clock distribution network design without requiring any change in placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.