Abstract: Information flow in the form of individual channels of digital data across a time division multiplex (TDM) bus is controlled when the bandwidth b.sub.c of an individual channel may not be integrally related to the bandwidth b.sub.t of individual time slots of the TDM bus. A channel is assigned to a selected number m of TDM bus time slots, where m=n and the relationship between b.sub.c and b.sub.t is given by the expression (n-1)b.sub.t <b.sub.c .mu.nb.sub.t. Sequential bytes of data from the channel are transmitted during data byte opportunities in the channel's selected time slots. A validity identification signal is generated for each data byte transfer opportunity in the selected time slots, and a predetermined binary state is transmitted substantially simultaneously with each data byte transfer opportunity. A VALID signal is transmitted, independently of the TDM bus, substantially simultaneously with each data byte transfer opportunity filled by the channel.

Abstract: A quad-port random access memory (RAM) is accessed simultaneously by a input-output (I/O) device, a digital signal processor (DSP), and a system bus with no need for any request/granted handshake. The I/O device, DSP, and system bus all constitute respectively different data transferring devices. The RAM is provided with three memory pages which are rotated logically by 120 degrees during successive time slots. The first memory page is accessed by the I/O device, the second memory page is accessed by the DSP, and the third memory page is accessed by the system bus during a first time slot. During subsequent time slots, the memory pages of the RAM are rotated logically so that data transfer is stepped through a predetermined sequence of data transferring device and memory page combinations in successive time slots so that all three data transferring devices are permitted to access the RAM at all times. The sequence continues repetitively during subsequent time slots.

Abstract: Apparatus provides time division multiplex (TDM) transmissions of interrupt requests between a plurality of shelves to a microprocessor mounted on one of the shelves. The shelves are interconnected with a cable wherein one lead is dedicated for the transmission of interrupt data signals to the microprocessor. Each shelf includes a plurality of ports or elements that are monitored and initiate interrupt request signals when a request for an action occurs therein for processing by the microcomputer. A separate encoder is mounted on each of the shelves for converting an interrupt request signal from an element on the same shelf into an X-bit interrupt data signal identifying that element. The bits of the X-bit interrupt data signal are serially transmitted over the one lead of the cable during a separate plurality of at least X clock cycles forming a timeslot assigned to the shelf originating the interrupt request within a frame period.

Abstract: A plurality of M PBXs are coupled to a plurality of N nodes forming a Distributed Transit Private Branch Exchange (PBX). The plurality of N nodes are located remotely from each other and form a wide area network. Each node is coupled to predetermined ones of the other nodes via separate links so that each node is able to communicate with all other nodes. One or more D-channel Server Modules (DSMs) are located in predetermined nodes of the plurality of N nodes. Each DSM is associated with a plurality of D channels which are each coupled to a separate interface device in the same node or different node by means of a link for receiving and transmitting signaling data to one of an associated predetermined PBX of the plurality of PBXs.

Abstract: A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various bus components in the same clock cycle. For example, the data source of one channel may issue a command on the command bus to its selected data destination to get ready to receive data while at the same time, a data source of a second channel actually transmits data on the data bus to its selected data destination. During the same clock cycle, a third data source can be selected by the arbitration bus to initiate or resume a channel.

Abstract: A networking node for interconnecting a local telephone switch such as a private branch exchange (PBX) with other such switches through other nodes, with respective internodal multichannel digital transmission links interconnecting the various nodes, provides service for both data and voice messages. The networking node provides at least two levels (one of which may be zero) of compression for voice messages and permits one of those levels to be preselected for all voice messages from the switch with which the node is associated to a predetermined one or more of the other nodes in the network. A look-up table is stored in memory within the node to control the assignment of particular levels of compression to particular destinations.

Abstract: A method of Distributed Call Control is provided in a Distributed Transit Private Branch Exchange (PBX) comprising a plurality of Nodes forming a wide area network, and a plurality of D-channel Server Modules (DSMs). The DSMs are located in predetermined ones of the Nodes with each DSM coupled to at least one associated PBX via at least one D channel. The method includes the following steps. First, a listing of all Exchange Codes (ECs) handled by a DSM and each associated PBX coupled thereto is stored in a local routing table of a memory in the DSM. Second, a listing of all ECs handled by all of the other DSMs of the Distributed Transit PBX and their associated PBXs is stored in a remote routing table of the memory in each of the DSMs.

Abstract: An apparatus uses parasitic capacitances between each of one or more leads and a spaced apart electrically conductive plane on a Printed Circuit Board (PCB) to store data transmitted on the one or more leads until new data is transmitted over the one or more leads from first or second devices interconnected by the one or more leads. The first device is responsive to a first control signal for modifying the data on the one or more leads and transmitting the modified data back onto the one or more leads. Alternatively, the first device is responsive to a second control signal for inhibiting the first device from reading the data from the one or more leads and from transmitting any data back onto the one or more leads for at least one clock cycle. When the first device is responsive to the second control signal, the data stored in the parasitic capacitances are, for example, read back into the second device and/or used as an output of the apparatus during a predetermined time period.

Abstract: A digital signal processing unit with an array of digital signal processors (DSP) is provided with a recirculation path for data sequences which cannot be fully processed by a single pass through the array. An input programmable gate array (PGA) controls distribution of data sequences to individual DSPs for processing and an output PGA controls their recollection. The recirculation path is provided by a recirculation register which is write enabled by the output PGA and read enabled by the input PGA.

Abstract: There is provided a method of adding a new private branch exchange interface (PBX port) to a data communication network having a number of existing PBX ports, each coupled to respective ones of data transport nodes for sending and receiving via high speed data links (e.g., T-1 lines) customer data to each of the other nodes. A network management system computer having a database is coupled to the network.

Abstract: A hardware circuit for protecting against the accidental writing in an area of memory which contains critical data. In order to access the critical data memory area during a write cycle, it is necessary first to control predetermined memory access cycles which include, for example, the writing of predetermined data at a predetermined address. After detection of such a "fictitious" write cycle, the hardware allows the next write cycle to access the critical data memory area.

Abstract: There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave processor can access only its respective memory, the master processor can access either its own memory or any one of the slave memories. Maximum throughput (efficiency) is achieved by suspending operation of a single slave processor for only a single memory cycle, i.e., the time required for the master processor to access the respective slave memory. Each processor/memory is on a single card, with all of the cards being connected to a common bus. The cards are virtually identical, and master/slave distinctions are determined by a single slot bit on each card. A unique addressing scheme is implemented for access from the master to a selected slave.