Abstract: A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.

Abstract: An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.

Abstract: A differential data transferring system and method uses three level voltages to simultaneously transfer three signals (for example, two data signals and one clock signal) across two transfer line sets (i.e., four transfer lines). Therefore, the differential data transferring method increases transferring efficiency by using fewer transfer lines. Also, according to the differential data transferring system and method, one of two transfer lines forming a transfer line set is controlled to a middle voltage level, while the other transfer line is controlled to either a high voltage or a low voltage. Accordingly, the voltage difference between the two transfer lines may be maintained at a constant amplitude. Additionally, the difference between first and second dividing voltages DC1 and DC2, which are used for generating a reference output data, is controlled to maintain a constant amplitude. Therefore, the differential data transferring system and method may provide improved operation reliability.

Abstract: A flat panel display device and a source driver circuit for the flat panel display device are provided for performing multiple driving operations within a unit sourcing period. In the flat panel display device, multiple driving operations are performed within the unit sourcing period, and source voltages are supplied to a selected number of data lines in each driving operation. In this case, one DAC is driven to generate source voltages for a plurality of data lines. In the flat panel display device, the number of the DACs is reduced and the overall layout area is greatly reduced. Also, standby power consumption can be greatly reduced due to the reduced number of amplifiers. Since the source voltages provided by the same amplifier are provided to adjacent data lines, a metal layer can be easily wired in the display panel.

Abstract: A source driver for display devices includes line pair driving blocks. Each of the line pair driving blocks includes a de-multiplexing portion for de-multiplexing first and second digital data to generate first and second de-multiplexing data, a decoding portion for decoding the first and second de-multiplexing data to generate first and second analog data, and a multiplexing portion for multiplexing the first and second analog data to generate first and second gradation voltages. In the source driver, the de-multiplexing portion is controlled by signals having information of loading timing for the digital data and information of polarity for the gradation voltages.

Abstract: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.

Abstract: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.

Abstract: A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.

Abstract: A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.

Abstract: A mixing type pixel driving method in an active display device includes generating a digital data for a selected pixel, first driving the selected pixel to be illuminated with a first illumination intensity, and second driving the selected pixel to be illuminated with a second illumination intensity in a second illumination interval. A relative ratio of the second illumination intensity to the first illumination intensity is changed according to the value of the digital data. The number of the converted bits by DAC is reduced. Therefore, the less bit DAC is adaptable for the mixing type pixel driving method and the layout area and the consumption current can be decreased.

Abstract: A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.

Abstract: An input buffer capable of achieving quick response. The input buffer includes first and second direct-current (DC) voltage controllers and first and second drivers. The first and second DC voltage controllers generate first and second alternating current (AC) signals having AC voltage components of the buffer input signal reflected thereon, respectively. The first driver drives the voltage level of a buffer output signal to the level of a first voltage, that is, a power supply voltage, in response to the first AC signal. The second driver drives the voltage level of a buffer output signal to the level of a second voltage, that is, a ground voltage, in response to the second AC signal. The first and second AC signals respond to a buffer input signal quickly. The first and the second drivers drive the levels of the buffer output signal to the power supply voltage level and the ground voltage level quickly and by a large amount.