Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
Type:
Grant
Filed:
July 28, 2022
Date of Patent:
August 20, 2024
Assignees:
TMicroelectronics Application GMBH, STMicroelectronics International N.V.