Patents Assigned to Toko, Inc.
  • Patent number: 5017950
    Abstract: A variable-capacitance diode element is disclosed which comprises a semiconductor substrate of a first conductivity type having an epitaxial layer of the first conductvity type provided on a main surface portion thereof, said epitaxial layer having a higher resistivity than that of said semiconductor substrate; a first diffusion layer of the first conductivity type diffused in said epitaxial layer and having a lower resistivity than that of said epitaxial layer; a second diffusion layer of a second conductivity type surrounded by said first diffusion layer and having a lower resistivity than that of said first diffusion layer; and a third diffusion layer of the second conductivity type of a small diffusion length covering an exposed portion of a major surface of said first diffusion layer and an exposed portion of a major surface of said diffusion layer. With such construction, the capacitance variation range of the diode element is widened, and the high-frequency serial resistance R.sub.
    Type: Grant
    Filed: January 17, 1990
    Date of Patent: May 21, 1991
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara
  • Patent number: 4987459
    Abstract: A variable-capacitance diode element having a wide capacitance variation range is disclosed which comprises an epitaxial layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type; a diffusion layer of the first conductivity type which is formed in the epitaxial layer with a higher concentration than said epitaxial layer by means of ion implantation; at least one diffusion layer of a second conductivity type which is formed in the diffusion layer of the first conductivity type so as to define PN junction; and a first-conductivity type buried layer of a low resistivity which is formed the boundary portion between the semiconductor substrate and the epitaxial layer where a depletion layer reaches which occurs in response to a reverse bias voltage being applied to the PN junction, whereby the depletion layer is caused to extend to a maximum possible effect.
    Type: Grant
    Filed: January 17, 1990
    Date of Patent: January 22, 1991
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara
  • Patent number: 4954850
    Abstract: In a variable-capacitance diode device consisting of a PN junction, and a semiconductor layer of a first conductivity type, the impurity concentration of which decreases as the depth from the PN junction increases, the semiconductor layer of the first conductivity type is arranged to include, except in the vicinity of the PN junction, at least one such point that the following relationship holds true:Ai.ltoreq.Ai+1 (i=1, 2, . . . , n)where Ai represents impurity concentration of said semiconductor layer of the first conductivity type at a distance Xi as viewed depth-wise of the PN junction.
    Type: Grant
    Filed: August 12, 1988
    Date of Patent: September 4, 1990
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara
  • Patent number: 4871958
    Abstract: In a charging circuit, a current correcting circuit is provided which includes a transistor, the collector current of which is permitted to flow through a resistor for setting up a reference voltage for a comparator circuit. The current correcting circuit is arranged such that when the output voltage of the charger goes below a predetermined level, the transistor is rendered conductive to compensate for the decrease in the reference current, thereby preventing the current from being decreased which flows through the resistor of the comparator circuit.
    Type: Grant
    Filed: December 18, 1987
    Date of Patent: October 3, 1989
    Assignee: Toko, Inc.
    Inventors: Hiroichi Ishikawa, Yasuo Nagasawa
  • Patent number: 4868134
    Abstract: A method of making a variable-capacitance diode device including semiconductor layer a first conductivity type in which the impurity concentration decreases with increasing depth from surface of a PN junction. The semiconductor layer of the first conductivity type is formed by diffusing an impurity element of the first conductivity type in a semiconductor substrate with a high degree of concentration. Thereafter, a semiconductor layer of a second conductivity type is formed which has such an impurity concentration profile that the concentration of impurity element of the second conductivity type is lower than the impurity concentration of said semiconductor layer of the first conductivity type formed in said semiconductor substrate and at a predetermined depth, the concentration of the second conductivity type impurity element is substantially equal or close to the concentration of the first conductivity type impurity element.
    Type: Grant
    Filed: August 17, 1988
    Date of Patent: September 19, 1989
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara
  • Patent number: 4847572
    Abstract: In an electronic tuning circuit for AM receiver including a radio-frequency tuning circuit and local oscillator circuit each using a variable capacitance diode, the local oscillator circuit comprises an oscillation coil; a padding capacitor connected in series with the oscillation coil; a first variable capacitance diode connected at one end in series with the oscillation coil; a first and a second fixed capacitor connected at one end in series with each other; and a second variable capacitance diode connected in parallel with the second fixed capacitor. The second fixed capacitor has its other end connected to a connection point between the padding capacitor and the first variable capacitance diode. The first fixed capacitor has its other end connected to the connection point between the oscillation coil and one end of the first variable capacitance diode. A tuning voltage is applied to the first and second variable capacitance diodes, thereby reducing tracking error over the entire receiving frequency band.
    Type: Grant
    Filed: October 28, 1987
    Date of Patent: July 11, 1989
    Assignee: Toko, Inc.
    Inventor: Hajime Yokoyama
  • Patent number: 4845454
    Abstract: An inductance element comprises at least one annular core formed by a magnetic foil belt wound in a volute form and comprising magnetic thin films deposited on a tape-like thin plate; and at least one wire wound on said core. The magnetic thin films are provided with an axis of easy magnetization directed in the direction of width of said magnetic foil belt. Further, the magnetic thin films are thicknesswise separated into a plurality of discrete layers by at least one intervening resistance layer having a resistivity in the range from 10.sup.2 .mu..OMEGA.. cm to 10.sup.6 .mu..OMEGA..cm. Alternatively, the core may be formed by plural pieces of magnetic foil belt comprising magnetic thin films deposited on a tape-like thin plate, said plurality pieces of magnetic foil belt being insulated from each other and provided in a laminated form.
    Type: Grant
    Filed: July 24, 1987
    Date of Patent: July 4, 1989
    Assignee: Toko, Inc.
    Inventors: Shigetoshi Watanabe, Takafumi Toda
  • Patent number: 4837852
    Abstract: An electronic tuning circuit for AM receiver is disclosed which is so designed that tracking errors are minimized by increasing the accuracy of constants for tuning coils, oscillation coils and capacitance elements incorporated in an antenna tuning circuit, a high-frequency amplifier circuit and a local oscillator circuit which constitute the electronic tuning circuit. After the electronic tuning circuit has been mounted in place, tracking adjustment is effected at one point of the receiving frequency band, or alternatively no such adjustment is required.
    Type: Grant
    Filed: June 13, 1986
    Date of Patent: June 6, 1989
    Assignees: Toko, Inc., Matsushita Electric Industrial Co., Ltd.
    Inventors: Noboru Takada, Hajime Yokoyama
  • Patent number: 4819144
    Abstract: A switching power supply circuit comprising a main switching element, and a second switching element which is on-off driven by the output of the main switching element. The design is made such that when the main switching element is turned on, the second switching element is turned off, while when the main switching element is turned off, the second switching element is turned on, and unwanted charges stored at the main switching element can be discharged through the second switching element when the main switching element is turned off.
    Type: Grant
    Filed: July 26, 1988
    Date of Patent: April 4, 1989
    Assignee: Toko, Inc.
    Inventor: Tetsushi Otake
  • Patent number: 4808856
    Abstract: A phase comparator which comprises a differential amplifier; and a first and a second active load circuit each comprising a current mirror circuit and from which is derived an output signal which is reversed in phase with respect to the output of the differential amplifier. The outputs of the respective active load circuits are superimposed upon each other through other current mirror circuits, and an output resulting from the superimposition is alternately provided based on rectangular waveform signals which are reversed in phase with respect to each other. By smoothing the output, a DC output corresponding to the phase shift of input signal from the rectangular waveform signals is produced. The phase comparator comprises a combination of transistors and diodes which are cascode-connected to each other, and thus is operable with a predetermined voltage as low a 1 V or less.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: February 28, 1989
    Assignee: Toko, Inc.
    Inventor: Hiroshi Tanigawa
  • Patent number: 4794650
    Abstract: A receiver equipped with an electronic tuning circuit which uses voltage-variable reactance elements such as variable-capacitance diodes or the like in the radio-frequency tuning circuit and oscillation tuning circuit thereof. The oscillation tuning circuit includes a novel padding capacitor constituted by a composite circuit of a variable-capacitance diode and fixed capacitors connected at the position where a conventional padding capacitor is connected. With such an arrangement, it is possible to make tracking error negligibly small over a frequency band ranging from a low receiving frequency to a high receiving frequency, by applying a tuning voltage to the composite padding capacitor.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: December 27, 1988
    Assignee: Toko, Inc.
    Inventor: Hajime Yokoyama
  • Patent number: 4767979
    Abstract: In a switching circuit device using current mirror circuits, there are provided a first group of current mirror circuits wherein a plurality of signal currents supplied via input terminals are superimposed upon mirror currents and signal currents resulting from the superimposition are derived as new mirror currents; and a second group of current mirror circuits to which the new mirror currents are supplied. The output stages of the second group of current mirror circuits are connected to each other at a common point which in turn is tied to the output stage of a current mirror circuit for supplying a mirror current of a predetermined magnitude. An output terminal is led out of said common point. Bias voltage for said second group of current mirror circuits is controlled so that any desired signal current is selected from said plurality of signal currents.
    Type: Grant
    Filed: July 1, 1987
    Date of Patent: August 30, 1988
    Assignee: Toko, Inc.
    Inventor: Hiroshi Tanigawa
  • Patent number: 4742569
    Abstract: In a tuning circuit for AM receiver, tuning coils, oscillation coils and capacitance elements of an antenna tuning circuit, a radio frequency amplifier circuit, and a local oscillator circuit are accommodated in discrete shield casings for high frequency coils; and the discrete shield casings are disposed in a row and united with each other in the form of blocks, thereby eliminating the necessity to effect tracking adjustment.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: May 3, 1988
    Assignees: Toko, Inc., Matsushita Electrical Industrial Co., Ltd.
    Inventors: Hajime Yokoyama, Noboru Takada, Yusuke Okamoto, Makoto Torakawa, Takashi Ikegame
  • Patent number: 4722027
    Abstract: In a hybrid circuit device comprising a base plate on which a circuit including coils is provided, and a flat package of integrated circuit having a smaller flat area than that of the base plate, the flat package and base plate are superimposed upon each other; the two circuits are connected together through terminals of the flat package; external terminals are connected to at least one of the two circuits; the hybrid circuit device is encapsulated with plastics as a whole, with the external terminals being exposed through the encapsulation; and on that part of the base plate which does not overlap the flat package, circuit components constituting the circuit provided on the base plate are securely mounted at lateral positions with respect to the flat package.
    Type: Grant
    Filed: August 5, 1986
    Date of Patent: January 26, 1988
    Assignee: Toko Inc.
    Inventor: Yasumitsu Hayakawa
  • Patent number: 4722041
    Abstract: An on-on type switching regulator comprises a blocking oscillator, rectifying-smoothing circuit, and a voltage drop circuit. The blocking oscillator includes a transformer having a collector winding, base winding and secondary winding, and a transistor. The rectifying-smoothing circuit comprises a rectifier diode, flywheel diode, choke coil, and smoothing capacitor, and is connected to the secondary winding. The voltage drop circuit is connected in a closed circuit which is formed between the base winding and the base-emitter of said transistor, said voltage drop circuit being arranged to block any forward or backward current when the voltage thereacross is in a micro-voltage range which may occur before excitation energy in the choke coil is discharged.
    Type: Grant
    Filed: October 28, 1986
    Date of Patent: January 26, 1988
    Assignee: Toko, Inc.
    Inventor: Hiroichi Ishikawa
  • Patent number: 4691120
    Abstract: In a pulse delay circuit device, a double-balanced type differential amplifier is provided which comprises a first and a second differential amplifier and is provided with a first and a second output stage. The design is made such that by rendering the differential amplifiers operative alternately, an output pulse having predetermined delay time and pulse width can be derived from each of the first and second output stages of the double-balanced type differential amplifier.
    Type: Grant
    Filed: October 28, 1986
    Date of Patent: September 1, 1987
    Assignee: Toko, Inc.
    Inventor: Hiroshi Kondo
  • Patent number: 4680528
    Abstract: A battery charging device which is so designed that whether or not the battery is connected in position can be detected by utilizing a current detecting circuit instead of a mechanically-structured component, such as a switch.
    Type: Grant
    Filed: March 4, 1986
    Date of Patent: July 14, 1987
    Assignee: Toko, Inc.
    Inventors: Toshio Mikami, Yasuo Nagasawa
  • Patent number: 4656442
    Abstract: A hybrid circuit device comprising a flat package incorporating an integrated circuit therein, and a delay line circuit constituted by a plurality of coils and a plurality of capacitors. A base plate supporting the delay line circuit is disposed on the flat package. First terminals which are upwardly bent and second terminals are led out of the flat package. The upwardly-bent terminals connect the integrated circuit and delay line circuit to each other at side portions of the base plate. Furthermore, separate external terminals, which are attached to the base plate and connected to the second terminals of the flat package, are provided in two rows holding the flat package therebetween. The device is encapsulated with the free end portion of each of the separate external terminals being exposed through the encapsulation at a position substantially equidistant from the top and bottom surfaces of the encapsulated device.
    Type: Grant
    Filed: February 13, 1985
    Date of Patent: April 7, 1987
    Assignee: Toko, Inc.
    Inventor: Yasumitsu Hayakawa
  • Patent number: 4642596
    Abstract: A miniaturized transformer which is constructed so that lead wires of a coil are first upwardly led out of the coil and then downwardly extended to be used as terminals for the transformer.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: February 10, 1987
    Assignee: Toko, Inc.
    Inventors: Shigeru Nakadai, Teruo Tamada
  • Patent number: 4641112
    Abstract: In a lumped constant type delay line device, conductive plates provided with connecting portions and terminals are insert-molded with respect to a plastic base plate in such a manner that the connecting portions are exposed at one surface of the base plate and the terminals extend externally of the base plate. The delay line device further includes capacitors connected to the connecting portions of the conductive plates; and coils having taps connected to electrodes provided on cores and connected to the terminals of the conductive plates, the coils being mounted on the other surface of the base plate.
    Type: Grant
    Filed: March 4, 1986
    Date of Patent: February 3, 1987
    Assignee: Toko, Inc.
    Inventor: Masami Kohayakawa