Patents Assigned to Tokyo Electron AT Limited
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Patent number: 11978655Abstract: A substrate transfer mechanism includes: an arm base main body provided with a first driver; a lift configured to move up and down the arm base main body; a first arm extending transversely from a lower side of the arm base main body, and having a tip end that pivots around a vertical axis with respect to the arm base main body by the first driver; a second arm extending transversely from an upper side of the tip end of the first arm, and having a tip end that pivots around a vertical axis with respect to the first arm along with the pivoting of the first arm; and a substrate holder provided on an upper side of the tip end of the second arm, and configured to rotate around a vertical axis with respect to the second arm.Type: GrantFiled: May 24, 2023Date of Patent: May 7, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Kousei Ide, Naruaki Iida
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Patent number: 11978735Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.Type: GrantFiled: April 14, 2022Date of Patent: May 7, 2024Assignee: Tokyo Electron LimitedInventors: Mark I. Gardner, Robert D. Clark, H. Jim Fulford
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Patent number: 11978644Abstract: A substrate processing system includes: a batch-type processing part that collectively processes a lot including substrates arranged at a first pitch; a single-substrate-type processing part that processes the substrates of the lot one by one; and an interface part that delivers the substrates between the batch-type processing part and the single-substrate-type processing part. The batch-type processing part includes a processing bath that stores a processing solution having a lump shape or a mist shape, a first holder that holds the substrates arranged at the first pitch, and a second holder that receives the substrates arranged at a second pitch from the first holder in the processing solution. The interface part includes a transfer part that transfers the substrates held separately by the first and second holders in the processing solution, from the batch-type processing part to the single-substrate-type processing part.Type: GrantFiled: August 12, 2022Date of Patent: May 7, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Kouzou Kanagawa, Kotaro Tsurusaki, Keiji Onzuka, Yoshihiro Kai
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Patent number: 11978631Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.Type: GrantFiled: December 9, 2020Date of Patent: May 7, 2024Assignee: Tokyo Electron LimitedInventors: Junling Sun, Katie Lutker-Lee, Angelique Raley, Andrew Metz
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Patent number: 11978614Abstract: A substrate processing apparatus includes a chamber having a plasma processing space, a sidewall of the chamber having an opening for transferring a substrate into the plasma processing space; and a shutter disposed at an inner side than the sidewall and configured to open or close the opening, the shutter having a flow path for a temperature-controlled fluid.Type: GrantFiled: June 17, 2020Date of Patent: May 7, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Yusuke Hayasaka, Jun Young Chung, Shuhei Yamabe, Keiichi Yamaguchi, Takehiro Tanikawa
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Patent number: 11978630Abstract: A heat treatment device includes: a heating plate configured to support and heat a substrate on which a resist film is formed; a chamber configured to cover a processing space above the heating plate; a gas supply configured to supply a gas into the chamber along a gas flow path connected to an inside of the chamber, the gas flow path beginning from an outer periphery of the heating plate and extending along an upper surface of the heating toward an end portion on an outer periphery of the substrate; and an exhaust port configured to evacuate inside of the chamber through exhaust holes that are formed above the processing space and open downwards.Type: GrantFiled: September 20, 2022Date of Patent: May 7, 2024Assignee: TOKYO ELECTRON LIMITEDInventor: Yohei Sano
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Publication number: 20240145595Abstract: A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: Tokyo Electron LimitedInventors: H. Jim Fulford, Mark I. Gardner
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Publication number: 20240145312Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming, on a first side of a substrate, a first stack and a second stack. The method includes etching, from the first side, a portion of the substrate interposed between the first and second stacks to form a recess. The method includes filling the recess with a dielectric material to form an isolation structure. The method includes forming, on the first side, one or more first interconnect structures over the first and second stacks. The method includes removing, from a second side of the substrate opposite to the first side, a remaining portion of the substrate. The method includes forming a via structure extending through at least the isolation structure. The method includes forming, on the second side, one or more second interconnect structures.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: Tokyo Electron LimitedInventors: Soo Doo Chae, Matthew Baron, Hojin Kim, Sunghil Lee
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Publication number: 20240145576Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: Tokyo Electron LimitedInventors: Mark I. Gardner, H. Jim Fulford, Partha Mukhopadhyay
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Publication number: 20240145218Abstract: The disclosed plasma processing apparatus is provided with a chamber, a substrate support, and a power source system. The substrate support has an electrode and configured to support a substrate in the chamber. The power source system is electrically connected to the electrode and configured to apply a bias voltage to the electrode to draw ions from a plasma in the chamber into the substrate on the substrate support. The power source system is configured to output a first pulse to the electrode in a first period and output a second pulse to the electrode in a second period after the first period, as the bias voltage. Each of the first pulse and the second pulse is a pulse of a voltage. A voltage level of the first pulse is different from a voltage level of the second pulse.Type: ApplicationFiled: December 27, 2023Publication date: May 2, 2024Applicant: Tokyo Electron LimitedInventor: Koichi NAGAMI
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Publication number: 20240143870Abstract: An information processing apparatus includes a generation unit that generates simulation data including a plurality of combinations of unprocessed data of a workpiece and processed data of the workpiece after a process is performed on the workpiece under a predetermined process condition. Each of the plurality of combinations includes the unprocessed data and the processed data when the process is performed with a plurality of pattern densities for each of a plurality of mask shapes. The information processing apparatus further includes a derivation unit that derives simulation parameters of a shape simulator based on a closeness between predicted data that is predicted by inputting the unprocessed data included in the simulation data to the shape simulator, and the processed data combined with the unprocessed data.Type: ApplicationFiled: October 30, 2023Publication date: May 2, 2024Applicant: Tokyo Electron LimitedInventors: Hironori MOKI, Tetsuya NISHIZUKA, Masanobu HONDA, Yusuke OGAWA
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Patent number: 11971144Abstract: A processing apparatus includes: a processing container configured to accommodate a substrate; a storage tank connected to the processing container via a gas supply pipe; a pressure sensor configured to detect a pressure in the storage tank; a valve provided in the gas supply pipe between the processing container and the storage tank; and a controller configured to control an opening degree of the valve based on the pressure in the storage tank detected by the pressure sensor.Type: GrantFiled: March 4, 2022Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventor: Seiya Nasu
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Patent number: 11969827Abstract: A processing apparatus configured to process a processing target object includes a holder configured to hold the processing target object; a holder moving mechanism configured to move the holder in a horizontal direction; a modifying device configured to radiate laser light to an inside of the processing target object to form multiple internal modification layers in a spiral shape; a modifying device moving mechanism configured to move the modifying device in the horizontal direction; and a controller configured to control an operation of forming the internal modification layers. The controller controls operations of the holder and the modifying device such that a spiral processing movement according to the formation of the internal modification layers and an eccentricity follow-up movement of correcting an eccentric amount between the holder and the processing target object held by the holder are shared by the holder and the modifying device.Type: GrantFiled: July 9, 2020Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Hayato Tanoue, Yohei Yamashita, Yohei Yamawaki, Hirotoshi Mori
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Patent number: 11970767Abstract: A method of forming a metal-containing nitride film containing silicon includes: supplying a metal-containing gas into a processing container in which a substrate is accommodated; supplying a silicon-containing gas into the processing container; and supplying a nitrogen-containing gas into the processing container, wherein a series of processes, in which the supplying the metal-containing gas and the supplying the silicon-containing gas are executed n times in this order (where n is an integer of one or more) and then the supplying the nitrogen-containing gas is executed, is repeated m times in this order (where m is an integer of one or more).Type: GrantFiled: August 10, 2020Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Taichi Monden, Tetsu Zenko, Kazuki Ota
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Patent number: 11970768Abstract: There is provided a method of forming a silicon nitride film on a substrate having first and second films formed thereon, wherein the first film and the second film have different incubation times. The method includes: supplying a processing gas composed of a silicon halide having Si—Si bonds to the substrate; supplying a non-plasmarized second nitriding gas to the substrate; forming a thin silicon nitride layer covering the first film and the second film by repeating the supplying the processing gas and the supplying the second nitriding gas in a sequential order; supplying a plasmarized modifying gas to the substrate and modifying the thin silicon nitride layer; and forming the silicon nitride film on the modified thin silicon nitride layer by supplying the raw material gas and the first nitriding gas to the substrate.Type: GrantFiled: August 14, 2020Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Hideomi Hane, Shimon Otsuki, Takeshi Oyama, Ren Mukouyama, Jun Ogawa, Noriaki Fukiage
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Patent number: 11969879Abstract: A substrate accommodating device accommodating a substrate transferred by a transfer device having an end effector configured to hold a substrate and a member including a consumable part disposed in a substrate processing apparatus for processing the substrate includes a container. A first opening through which the end effector holding the substrate passes is formed on a sidewall of the container. A recess into which front ends of the end effector are inserted is formed on an inner surface of the container facing the first opening.Type: GrantFiled: February 28, 2022Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventor: Masahiro Dogome
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Patent number: 11972958Abstract: A substrate processing apparatus includes a processing tub configured to perform an etching processing therein by immersing multiple substrates in a processing liquid; a first and second discharge opening groups disposed under the substrates within the processing tub, and configured to discharge the processing liquid into the processing tub; a first adjusting device configured to change a flow rate of the processing liquid discharged from the first discharge opening group; a second adjusting device configured to change a flow rate of the processing liquid discharged from the second discharge opening group; a controller configured to control the first and second adjusting devices to perform, during the etching processing, a flow rate adjusting processing of increasing and decreasing the flow rate of the processing liquid discharged from the first discharge opening group and the flow rate of the processing liquid discharged from the second discharge opening group to different values.Type: GrantFiled: May 12, 2021Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Takumi Honda, Hiroyuki Masutomi
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Patent number: 11972921Abstract: A temperature measurement system includes: a thickness calculating unit that calculates an optical thickness of a substrate; a rotation position detecting unit that detects rotation position information of the rotary table; a substrate specifying unit that specifies a substrate based on the rotation position information; a storage unit that stores first relationship information indicating a relationship between a temperature and a thickness associated with each substrate, and second relationship information indicating a relationship between an amount of change in temperature and an amount of change in optical thickness associated with each substrate; and a temperature calculating unit that calculates a temperature of the substrate based on the optical thickness calculated by the thickness calculating unit, the substrate specified by the substrate specifying unit, the first relationship information, and the second relationship information.Type: GrantFiled: November 5, 2020Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Takeshi Kobayashi, Tatsuo Matsudo
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Patent number: 11970778Abstract: A processing apparatus includes: a processing container having a substantially cylindrical shape; a gas supply pipe configured to supply a gas into the processing container; and an exhaust duct extending in a longitudinal direction of the processing container to form an exhaust window configured to exhaust the gas from an interior of the processing container, a first exhaust flow path configured to exhaust, from a first side in a longitudinal direction of the exhaust window, the gas exhausted through the exhaust window, and a second exhaust flow path configured to exhaust, from a second side in the longitudinal direction of the exhaust window, the gas exhausted through the exhaust window, wherein the exhaust duct includes: a first gas introduction part configured to introduce a ballast gas into the first exhaust flow path, and a second gas introduction part configured to introduce the ballast gas into the second exhaust flow path.Type: GrantFiled: February 7, 2022Date of Patent: April 30, 2024Assignee: Tokyo Electron LimitedInventor: Reita Igarashi
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Patent number: 11972925Abstract: A plasma processing apparatus includes: a plasma processing chamber; a substrate support disposed in the plasma processing chamber and including a lower electrode; a source RF generator coupled to the plasma processing chamber and configured to generate a source RF signal including high states and low states in alternate manner; and a bias DC generator coupled to the lower electrode and configured to generate a bias DC signal including ON states and OFF states in alternate manner. Each ON state includes a plurality of cycles, each cycle including a first sequence of first pulses and a second sequence of second pulses, each first pulse having a first voltage level, and each second pulse having a second voltage level different from the first voltage level.Type: GrantFiled: May 7, 2021Date of Patent: April 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Bong seong Kim, Ken Kobayashi, Mitsunori Ohata, Yoon Ho Bae