Abstract: Image display systems comprising a first pixel, a second pixel, a scan line, a first data line, and a second data line. In the first pixel, a first transistor is coupled to a first storage capacitor via a first pixel electrode. In the second pixel, a second transistor is coupled to a second storage capacitor via a second pixel electrode. The conductance of the first and second transistors is simultaneously controlled by a scan signal transmitted by the scan line. In a first time interval, the first data line transmits a voltage data to the first pixel electrode via the first transistor. In a second time interval, the second data line transmits the voltage data to the second pixel electrode via the second transistor. The first storage capacitor is designed to generate a proper feedthrough voltage at the first pixel electrode to compensate for a voltage coupling shift at the first pixel electrode that is generated during the second time interval because of the voltage variation at the second pixel electrode.

Abstract: Image display techniques for eliminating mura defects, which collects reference data and adjusts the gray levels. The image display systems comprising a plurality of pixels, a memory, and an ASIC. Each of the pixels relates to a mura compensation coefficient set. The mura compensation coefficient sets of the pixels are generated by a coefficient generator. The memory stores the mura compensation coefficient sets of the pixels. The ASIC reads the mura compensation coefficient sets from the memory. With different mura compensation coefficient sets, the ASIC serves as different mura compensation function sets. Each mura compensation function set relates to one of the aforementioned pixels and is used for transforming an original gray level to a mura-eliminated gray level to drive the corresponding pixel.