Abstract: Disclosed is a data processing system using a dual monitor, on which separate contents are displayed respectively, as a display device. The data processing system includes: a memory providing a data processing area using programs; an input device for inputting data; a first VGA generating screen data for a result processed by programs; a second VGA generating screen data for a result processed by programs and different from the contents displayed by the first VGA; a processor processing data input through the input device using the memory and outputting the processed result through the first and second VGAs; a first monitor for displaying screen data from the first VGA; and a second monitor for displaying screen data from the second VGA.

Abstract: An authentication system and method therefor is provided, in which a dedicated system is installed to allow only a computer system which is monopolistically and exclusively supplied by a company operating an information providing server to be used to access the server. Here, the user computer includes an authentication system which generates a specific registration code for the system. The authentication system includes the user computer for generating a registration code for authenticating the user computer, and a system server which receives the registration code of the user computer and ascertains whether or not the user computer is registered.

Abstract: Disclosed is a video signal processing system for outputting video signals for driving monitors during one period of clock signal. The system includes: a clock signal (CLK) supply part for outputting CLK for transmitting video signal; a monitor controller for outputting memory access signal (MA) by the period of CLK; a memory buffer for outputting data signal according to MA; latch circuits for latching data signal, dividing into multiple data during one period of CLK and outputting the latched data to the monitors; an inverter inverting CLK; a delay circuit delaying inverted CLK; and a flip-flop circuit for outputting in flip-flop after receiving delayed CLK and inputting into the latch circuits.