Abstract: The present invention provides a method for hardware reduction in the echo canceller and the near-end crosstalk canceller. The method applies an N (N is a positive integer) times divide frequency sampling operation onto the input data list of the echo canceller first (and the near-end crosstalk canceller). Then, it applies an N times multiply frequency sampling operation onto the output data list of the echo canceller (and the near-end crosstalk canceller) to generate a multiplied frequency data list. Afterwards, a low pass filter operation is applied to the multiplied frequency data list to generate a low pass data list to eliminate the echo signal (and the near-end crosstalk signal). The present invention reduces the number of the taps in the echo canceller and the near-end crosstalk canceller by using the digital signal process technique. Therefore, the area of the whole communication IC occupied by the echo canceller and the near-end crosstalk canceller can be reduced.

Abstract: An apparatus of a digital echo canceller comprises a first-set delay circuits, a selector, a second-set delay circuits, a plurality of multipliers and an adder. The first-set delay circuits are arranged into groups, and each group has N delay circuits. An exhaustive search function is carried out to produce a plurality of energy sums. The selector will select the biggest energy sum to serve as a significant part and then transmit to the outputs of the second-set delay circuits, the multipliers and the adder. An estimated echo signal is produced to cancel the echo signal.

Abstract: An apparatus of a digital echo canceller and method therefor, a designed selector is used values of receiving and input signals to estimate the length of a cable. The response values of an insignificant part of the echo signal can be selected. Multiplication and addition operations are carried out in a response region of a significant part of the echo signal. An estimated echo signal is produced to cancel the echo signal, unnecessary operations and the cost of a hardware can be reduced.

Abstract: A network connection device having internal circuitry capable of wiring correctly to a network cable is described. The network connection device includes an interface circuit, a switching array and a controlling circuit. First, the network connection device is physically connected to the network cable. Next, the positive and negative receiving terminals in the interface circuit are connected to a pair of signal carrying wires through the device's internal circuitry. Depending on the returned preamble field, the connections to the signal-carrying wires are judged to be either incorrect, in which case the connection has to be swapped through device's internal circuitry, or correct, in which case no swapping is required. Subsequently, the positive and negative transmission terminals are connected to a second pair of wires inside the network cable. Next, a data packet is sent out through the transmission terminal.

Abstract: A comparator circuit used in an analog-to-digital converter includes an input voltage signal line; a reference voltage signal line; a plurality of comparators connected to said input voltage signal line and said reference voltage signal line; a plurality of amplifiers corresponding separately to each of said plurality of comparators and connected respectively between said input voltage signal lines, said reference voltage signal lines, and their corresponding comparators; and a thermocode channel connected to outputs of said plurality of comparators. A plurality of resistors with resistances in a constant ratio are provided in said reference voltage signal line and each is connected between the inputs of two adjacent amplifiers. A plurality of averaging resistors are provided and each is connected between the drains of the input transistor of two adjacent comparators; wherein said plurality of averaging resistors have the same resistance.

Abstract: A comparator circuit used in an analog-to-digital converter includes an input voltage signal line; a reference voltage signal line; a plurality of comparators connected to said input voltage signal line and said reference voltage signal line; a plurality of amplifiers corresponding separately to each of said plurality of comparators and connected respectively between said input voltage signal lines, said reference voltage signal lines, and their corresponding comparators; and a thermocode channel connected to outputs of said plurality of comparators. A plurality of resistors with resistances in a constant ratio are provided in said reference voltage signal line and each is connected between the inputs of two adjacent amplifiers. A plurality of averaging capacitors are provided and each is connected between the outputs of two adjacent comparators; wherein said plurality of averaging capacitors may have the same capacitance.

Abstract: A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth negative phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch, a fifth positive phase logic switch, a first current source circuit, a second current source circuit and a control logic circuit. Using the first and the second current source circuits, a self-calibration can be performed while the high speed comparator is just turned on, so that the input offset voltage of the high speed comparator can be eliminated.

Abstract: A voltage-controlled oscillator comprising a voltage compensation transistor is disclosed. The voltage compensation transistor is able to provide an equivalent resistance to the bias voltage supplied to the oscillator. When a sudden raise in the voltage of the power supply takes place, the equivalent resistance of the compensation transistor will drop, such that the bias voltage supplied to the oscillator may be pulled down, whereby the oscillation frequency of the ring oscillator may be adjusted.

Abstract: A pre-charged high-speed comparator includes a first negative phase logic switch, a second negative phase logic switch, a third negative phase logic switch, a first positive phase logic switch, a fourth negative phase logic switch, a second positive phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch and a fifth positive phase logic switch. The two output terminals of the pre-charged high-speed comparator is raised to a voltage roughly half of a source voltage so that the time required for a regeneration circuit that includes the third negative phase logic switch, the first positive phase logic switch, the fourth negative phase logic switch and the second positive phase logic switch to get into the transistor active region is shortened, thereby increasing the overall operating speed of the comparator circuit.