Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.

Abstract: A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: There are disclosed a method and apparatus for reordering sequenced data packets. An expiration time is calculated for each received data packet. The expiration time and a packet sequence number are stored in a table. The table is read to determine the next data packet to be transmitted in sequence number order. The next data packet is output if available. If the next data packet is not available, a true expiration time is determined for the unavailable next data packet. If the unavailable next data packet fails to arrive before a current time is greater than the expiration time of the unavailable data packet, the unavailable next data packet is considered lost.

Abstract: System for reordering sequenced based packets in a switching network. The system includes time stamp logic that operates to associate a receive time indicator with each received data packet. The system also includes Enqueue logic that operates to compute an expiration time for each received packet based on the receive time indicator, and stores the expiration time and the sequence identifier for each received packet into a table. Dequeue logic operates to read the table to determine the received data packets to output in an output stream so that the received data packets are output in a selected order. The Dequeue logic also operates to determine a true expiration time for one or more unreceived data packets, and if the true expiration time for a selected unreceived data packet is reached, the Dequeue logic operates to omit the selected unreceived data packet from the output stream.

Abstract: System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. There may be defined a number of portions of the address space. There may be groups of the portions, and data units addressed to one portion within the group may be re-addressed to the other portions.

Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.

Abstract: Variable length switch fabric for switching variable length data packets between input and output transmission paths in a communication network. In one embodiment of the invention, apparatus is provided for switching variable length data packets between input and output transmission paths in a communication network. The apparatus includes a plurality of input ports coupled to receive the plurality of variable length data packets from the input transmission paths and a plurality of output ports coupled to transmit the plurality of variable length data packets on the output transmission paths. The apparatus also includes a variable length switch fabric coupled to the plurality of input ports and the plurality of output ports, the variable length switch fabric operates to switch the plurality of variable length data packets from selected input ports to selected output ports in an unsegmented form.