Abstract: A high-density memory system includes at least one memory-dense compute unit with a printed circuit board (“PCB”) having a half-width one rack unit (“1U”) form factor, more than 20 memory module slots arranged depth-wise from a front to a rear of the PCB with a horizontal orientation that is parallel to the half-width 1U form factor, at least one processor positioned in between the memory module slots, a dripless connector with a first port that receives a cooling solution from a manifold of a cooling unit and a second port that returns the cooling solution into the manifold, tubing that extends the full length of the PCB from the first port past the memory module slots and the at least one processor and back to the second port, and cooling blocks that are located in between the memory module slots and that are connected to the tubing.

Abstract: Provided is a disaggregated memory server, which in some examples is a rack-mounted hardware appliance comprising a pool of memory for allocation to memory clients. Examples of memory clients may include one or more rack-mounted computing devices co-located on a rack with the disaggregated memory server. The disaggregated memory server may be optimized for high-speed dynamic memory allocation to the other computing devices in the rack.

Abstract: Disclosed is a controller for a disaggregated memory device. The controller may receive a request to allocate memory of a specific size from the disaggregated memory device to a computing device, and may generate a memory block device in the specific size from a memory pool formed from physical memory modules configured on the disaggregated memory device. The controller may expose the memory block device to the computing device as a Non-Volatile Memory Express (“NVMe”) target device, and may control access to the memory block device by converting NVMe access requests in a first format from the computing device to access requests in a different second format supported by the memory block device.

Abstract: Disclosed is a controller for a disaggregated memory device. The controller may receive a request to allocate memory of a specific size from the disaggregated memory device to a computing device, and may generate a memory block device in the specific size from a memory pool formed from physical memory modules configured on the disaggregated memory device. The controller may expose the memory block device to the computing device as a Non-Volatile Memory Express (“NVMe”) target device, and may control access to the memory block device by converting NVMe access requests in a first format from the computing device to access requests in a different second format supported by the memory block device.

Abstract: Disclosed is a controller for providing applications seamless access to local and remote memory so that data of a particular application that is moved out of the Random Access Memory (“RAM”) of a local device may be stored and accessed in RAM of a remote device rather than on higher latency and slower performing storage mediums. The controller provides an application with a first allocation of RAM from the local device running the application, and a second allocation of RAM from the remote device. The controller registers to receive a page fault notification for a particular page that the application attempts to access and that is not stored in the first allocation of RAM. The controller retrieves the particular page from the second allocation of RAM, and loads it into the first allocation of RAM where it becomes accessible by the application.