Abstract: A throttled data pipeline having a limited data-transfer rate for conserving system resources is disclosed. The throttled data pipeline of the present invention includes a source, a destination and a throttling device. The throttling device of the present invention is interposed between the source and the destination, and is adapted to limit data-transfer rates through the throttled data pipeline in accordance with predetermined criteria. By limiting data-transfer rates through the throttled data pipeline, system resources of the host computer, which would otherwise be wasted, are conserved. The throttled data pipeline of the present invention is configured to allow for fast and efficient transfers of data during low throughput operations when system resources are not significantly taxed.

Abstract: In a machine having facsimile capabilities, a method for programming soft speed buttons which includes determining whether a number is associated with a given speed button; and if a number is associated with that speed button, providing for a facsimile message to be transmitted to the associated phone number. However, if no number is associated with the given speed button, then allowing a user to create a label for that speed button, and also to associate a number with that speed button.

Abstract: A throttled data pipeline having a limited data-transfer rate for conserving system resources is disclosed. The throttled data pipeline of the present invention includes a source, a destination and a throttling device. The throttling device of the present invention is interposed between the source and the destination, and is adapted to limit data-transfer rates through the throttled data pipeline in accordance with predetermined criteria. By limiting data-transfer rates through the throttled data pipeline, system resources of the host computer, which would otherwise be wasted, are conserved. The throttled data pipeline of the present invention is configured to allow for fast and efficient transfers of data during low throughput operations when system resources are not significantly taxed.

Abstract: An application specific integrated circuit (ASIC)/field programmable gate array (FPGA) which is a component of a wireless LAN controller including a local processor and a memory enables the controller to interface with both PCMCIA.TM. and AT.TM. host computer systems. The ASIC/FPGA enables communication between a radio frequency communication module, a local processor, and the host computer. The ASIC/FPGA also includes a throttle feature that decreases the access of the host computer in comparison to access of the local processor in order to enable the local processor to rapidly generate an acknowledge signal as required by various RF LAN specifications. During operation of the controller, data to be transmitted by the host computer onto the network is written by the host to an SRAM via the ASIC/FPGA, and the host commands the local processor via the ASIC/FPGA to forward the transmitted data to the RF communication module.