Patents Assigned to Toshiba Corporation
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Patent number: 9608103Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.Type: GrantFiled: October 2, 2014Date of Patent: March 28, 2017Assignee: Toshiba CorporationInventors: Jeffrey Craig Ramer, Karl Knieriem
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Patent number: 9606915Abstract: The operation of a pool of solid state drives is orchestrated to manage garbage collection and wear leveling. Each individual solid state drive is operated in either an Active Mode in which I/O commands are processed or in a Maintenance Mode in which garbage collection is performed and no I/O commands are processed. The selection of solid state drives in the Active Mode is further selected to achieve wear leveling over the pool of solid state drives. A virtualization layer provides dynamic mapping of virtual volume addresses to physical solid state drives.Type: GrantFiled: August 11, 2015Date of Patent: March 28, 2017Assignee: Toshiba CorporationInventors: Nigel D. Horspool, Yaron Klein
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Patent number: 9585243Abstract: Methods of manufacturing circuit boards and circuit boards formed thereby to have a surface that is configured to receive circuitry and a notch of a selectable configuration in a lateral edge along the surface of the circuit board boards, and where the selectable configuration is configured to convey identifying information relating to the circuit boards. Such a circuit board can be produced from a panel containing one or more circuit boards, wherein at least one circuit board has a border adjoined and defined by a partition feature that is configured to enable the circuit board to be physically separated from other portions of the panel. Notches having the same of varying selectable configurations may be formed on the at least one circuit board during the manufacturing of the circuit board.Type: GrantFiled: December 23, 2015Date of Patent: February 28, 2017Assignee: Toshiba CorporationInventors: Stephen K. Pardoe, Nigel Rowe
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Patent number: 9558839Abstract: A solid state drive has a power failure savings mode that permits a reduction in holdup time for a temporary backup power supply. The solid state drive stores data in a multi-level cell (MLC) mode. In a power fail saving mode system metadata is written in a pseudo Single Level Cell (pSLC) mode. In the normal operating mode page writes are performed in complete blocks. In the power fail save saving mode data from a write buffer is written and additional dummy pages written to reduce the total number of pages that must be written to below a complete block size with the dummy pages providing protection from data corruption.Type: GrantFiled: March 9, 2015Date of Patent: January 31, 2017Assignee: Toshiba CorporationInventors: Leland W. Thompson, Christopher S. Delaney, Gordon W. Waidhofer, Ali Aiouaz
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Patent number: 9553483Abstract: A system and method thereof to regulate a current to a capacitive load from a power supply connected to the capacitive load. The system includes a first switch between the power supply and the capacitive load, a super-capacitor configured for charging by the power supply and powering the capacitive load, a current limiting circuit between the super-capacitor and the power supply, a second switch between the super-capacitor and the capacitive load, and a power control circuit configured to control opening and closing of the first switch and the second switch independently, sense a voltage of the power supply, and sense a voltage of the super-capacitor.Type: GrantFiled: March 3, 2014Date of Patent: January 24, 2017Assignee: Toshiba CorporationInventors: Wenwei Wang, Karl Reinke
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Patent number: 9553181Abstract: The present disclosure presents a novel structure for a dielectric material for use with Group III-V material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a III-V material where the dielectric layer comprises a first region in contact with the top surface of the III-V material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer. The dielectric layer has material properties different from traditional dielectric layers as it is composed of both crystalline and amorphous structures. The crystalline structure is at the interface with the III-V material (such as AlGaN or GaN) but gradually transitions into an amorphous structure, both within the same layer and both comprising the same material.Type: GrantFiled: June 1, 2015Date of Patent: January 24, 2017Assignee: Toshiba CorporationInventor: Long Yang
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Patent number: 9542119Abstract: Methods for providing non-volatile solid-state mass storage media with different service levels for different types of data associated with different applications. The method includes partitioning the non-volatile solid-state mass storage media into at least first and second volumes, individually assigning different service levels to the first and second volumes based on a type of data to be stored in the first and second volumes and based on the first and second volumes having different data retention requirements and/or data reliability requirements, and then performing service maintenance on data stored within at least the first volume according to the service level of the first volume.Type: GrantFiled: July 9, 2014Date of Patent: January 10, 2017Assignee: Toshiba CorporationInventor: Yaron Klein
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Patent number: 9490392Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.Type: GrantFiled: October 20, 2015Date of Patent: November 8, 2016Assignee: Toshiba CorporationInventor: Steve Ting
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Patent number: 9477630Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.Type: GrantFiled: February 7, 2014Date of Patent: October 25, 2016Assignee: Toshiba CorporationInventors: Karl Reinke, Dokyun Kim, William Allen
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Patent number: 9465737Abstract: A memory system includes a cache module configured to store data. A duplicate removing filter module is separate from the cache module. The duplicate removing filter module is configured to receive read requests and write requests for data blocks to be read from or written to the cache module, selectively generate fingerprints for the data blocks associated with the write requests, selectively store at least one of the fingerprints as stored fingerprints and compare a fingerprint of a write request to the stored fingerprints.Type: GrantFiled: June 19, 2013Date of Patent: October 11, 2016Assignee: Toshiba CorporationInventors: Sandeep Karmarkar, Paresh Phadke
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Patent number: 9455053Abstract: A method of providing an end-capped tubular ceramic composite for containing nuclear fuel (34) in a nuclear reactor involves the steps of providing a tubular ceramic composite (40), providing at least one end plug (14, 46, 48), applying (42) the at least one end plug material to the ends of the tubular ceramic composite, applying electrodes to the end plug and tubular ceramic composite and applying current in a plasma sintering means (10, 50) to provide a hermetically sealed tube (52). The invention also provides a sealed tube made by this method.Type: GrantFiled: September 16, 2013Date of Patent: September 27, 2016Assignees: Westinghouse Electric Company LLC, KABUSHIKI KAISHA TOSHIBA AKA Toshiba CorporationInventors: Peng Xu, Edward J. Lahoda, Lars Hallstadius, Joon Hyung Choi, Shinichi Higuchi, Fumihisa Kano
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Patent number: 9437776Abstract: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed.Type: GrantFiled: November 20, 2013Date of Patent: September 6, 2016Assignee: Toshiba CorporationInventors: Chao-Kun Lin, Heng Liu
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Patent number: 9417819Abstract: A solid-state mass storage device adapted to be used as a cache for an hard disk drive that utilizes a more efficient logical data management method relative to conventional systems. The storage device includes a circuit board, a memory controller, at least one non-volatile memory device, and at least two data interfaces. The storage device is coupled to a host computer system and configured to operate as a cache for at least one hard disk drive. The storage device is interposed between the host computer system and the at least one hard disk drive. Both the storage device and the at least one hard disk drive are coupled to the host computer system through a single connection and configured to operate in a daisy chain configuration.Type: GrantFiled: November 13, 2013Date of Patent: August 16, 2016Assignee: Toshiba, CorporationInventors: Stephen Jeffrey Smith, Franz Michael Schuette
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Patent number: 9391234Abstract: A light source and method for making the same are disclosed. The light source includes a conducting substrate, and a light emitting structure that is divided into segments. The light emitting structure includes a first layer of semiconductor material of a first conductivity type deposited on the substrate, an active layer overlying the first layer, and a second layer of semiconductor material of an opposite conductivity type from the first conductivity type overlying the active layer. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first layer in the first segment to the second layer in the second segment. A power contact is electrically connected to the second layer in the first segment, and a second power contact electrically connected to the first layer in the second segment.Type: GrantFiled: July 30, 2015Date of Patent: July 12, 2016Assignee: Toshiba CorporationInventors: Steven D. Lester, Chih-Wei Chuang
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Patent number: 9384155Abstract: The present disclosure includes systems and techniques relating to customization of a bus adapter card. in some implementations, an apparatus includes a processor and a program memory, a bus adapter card coupled with the computing apparatus and configured to connect with a storage device, the bus adapter card computing a cache memory and a controller to cache in the cache memory data associated with the storage device, where the program memory includes a driver to communicate with the bus adapter card responsive to requests corresponding to the storage device, and the driver is configured to modify its communications with the bus adapter card responsive to information provided separate from the requests.Type: GrantFiled: January 10, 2014Date of Patent: July 5, 2016Assignee: Toshiba CorporationInventors: Arvind Pruthi, Ram Kishore Johri
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Patent number: 9385001Abstract: A P-N junction gate high electron mobility transistor (HEMT) device with a self-aligned gate structure and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. A gate layer is formed on the barrier layer, the gate layer comprising a P-type group III-V semiconductor material suitable for depleting the carriers of a current conducting channel at the heterojunction when the HEMT device is off. A gate electrode comprising indium tin oxide (ITO) is formed on the gate layer, the gate electrode and the gate layer having substantially the same length.Type: GrantFiled: March 17, 2015Date of Patent: July 5, 2016Assignee: Toshiba CorporationInventors: Yongxiang He, Xinyu Zhang
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Patent number: 9359165Abstract: According to an embodiment, there is provided a sheet processing apparatus including a contactless type detection magnetic sensor for detecting magnetism of a sheet, correction magnetic sensors for detecting a magnetic field near the detection magnetic sensor, coils arranged near the detection magnetic sensor, and a cancel device for generating a cancellation magnetic field for cancelling a magnetic field near the detection magnetic sensor from the coils based on a detection result of the correction magnetic sensors.Type: GrantFiled: March 10, 2015Date of Patent: June 7, 2016Assignee: Toshiba CorporationInventor: Youyang Ng
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Patent number: 9357157Abstract: In a transmission side, a layer adjusting unit performs an adjustment to store a scalable encoded video data in a memory, select and output a scalable data of a base quality as a real-time video, read from a memory a scalable data of an enhancement quality based on the designation of a enhancement quality and a transmission period of time, and output the scalable data of an enhancement quality together with a real-time scalable data. In the receiving side, a layer synthesizing unit synthesizes and outputs a real-time video at normal times, and lowers the real-time video to a quality of the base layer if there is an enhancement quality video of a designated period of time, thereby reading the base quality layer data corresponding to the designated video from the memory (153) and synthesizing the data with the enhancement quality video to output the resulting data.Type: GrantFiled: October 21, 2011Date of Patent: May 31, 2016Assignee: Toshiba CorporationInventors: Sunao Wada, Yasuo Ohya, Shunichi Gondo
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Patent number: 9342120Abstract: A mounting structure adapted for mounting an expansion card within a computer enclosure and configured to directly absorb and conduct heat from a heat source (such as an IC chip) on the card to the ambient atmosphere surrounding the enclosure. The mounting structure includes a mounting bracket, a heat sink adapted to contact a surface of the heat source on the expansion card, an extension interconnecting the heat sink and the mounting bracket, one or more features for conducting heat from the heat sink to the mounting bracket, and one or more features associated with the mounting bracket for dissipating heat from the mounting structure to the ambient atmosphere surrounding the enclosure.Type: GrantFiled: August 13, 2014Date of Patent: May 17, 2016Assignee: Toshiba CorporationInventors: Dokyun Kim, Karl Reinke
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Patent number: 9324697Abstract: The present disclosure provides a novel light-emitting diode package and corresponding fabrication method for making such a package. The novel LED package comprises a resin carrier layer having a first and second surface. Embedded in the resin carrier layer are at least one electrical conductor and at least one LED. The embedded LED comprises a substrate having a bottom surface that is substantially exposed at the second surface of the resin carrier layer. The embedded LED further comprises a light emitting layer that is substantially exposed at the first surface of the resin carrier layer.Type: GrantFiled: March 16, 2015Date of Patent: April 26, 2016Assignee: Toshiba CorporationInventors: Chao-Kun Lin, Norihito Hamaguchi