Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.

Abstract: A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.

Abstract: A semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells; a first word line coupled to gates of the first and fifth memory cells; a second word line coupled to gates of the second and sixth memory cells; a third word line coupled to gates of the third and seventh memory cells; and a fourth word line coupled to gates of the fourth and eighth memory cells. In a write operation, writes to the fourth memory cell, the first memory cell, the eighth memory cell, and the fifth memory cell are executed in order.