Abstract: According to one embodiment, a semiconductor memory device, includes a memory cell comprising a switching element and a resistance change element; and a first circuit that applies a first voltage to the memory cell, places the memory cell into an ON state by applying a second voltage to the memory cell while applying the first voltage to the memory cell in parallel, generates a third voltage based on a resistance state of the resistance change element by performing first voltage application to perform a first readout on the memory cell in the ON state, writes first data into the memory cell.

Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: A storage array includes a first controller, memory, and one or more storage devices. Each of the storage devices comprises a second controller and a nonvolatile memory. The first controller receives a command and data from a host connected to the storage array and transmits a response or data to the host. When a write command, write data, and size information of the write data are received from the host, the first controller sends the received data to the second controller. The second controller determines a write address indicating a memory region of the nonvolatile memory in which the write data are to be written, based on the write command and the size information, writes the write data in the memory region associated with the write address, and transmits the write address to the first controller. The first controller further transfers the write address to the host.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on soft decoding errors in connection with a first read operation on the flash memory. The circuit may be further configured to generate estimated soft information based on the estimated slope information. The circuit may be further configured to decode a result of a second read operation on the flash memory based on the estimated soft information.

Abstract: According to one embodiment, an imprinting method comprises forming a carbon film on a substrate. The carbon film being oxygen in an amount of less than or equal to 15% by weight. A transfer material is dispensed over the carbon film. A patterned template is brought into contact with the transfer material. The transfer material is cured with light passing through the patterned template. The patterned template is then detached from the cured transfer material.

Abstract: A memory system includes a semiconductor storage device and a memory controller. The memory controller includes a command buffer and a descriptor buffer. The memory controller stores a first command received from outside in the command buffer, fetches a first descriptor from the host device, based on the stored first command, stores the fetched first descriptor in the descriptor buffer, stores a second command received from the outside in the command buffer, discards an unused part of the first descriptor from the descriptor buffer, fetches a second descriptor from the host device, based on the stored second command, and stores the fetched second descriptor at an address where the discarded part of the first descriptor was stored.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film that contains carbon on the first film, and processing the second film into a second pattern. The method further includes impregnating a metal element or a semiconductor element into the second pattern after the processing into the second pattern. The method further includes processing the first film into a first pattern using the second pattern after the impregnation of the metal element or the semiconductor element.

Abstract: A semiconductor memory device includes first and second bit lines, first and second memory transistors connected to the respective first and second bit lines, a source line connected to the first and second memory transistors, and a word line connected to gate electrodes of the first and second memory transistors. In an erase operation that erases data in the first and second memory transistors: a first erase voltage application operation is performed; an erase verify operation is performed on only one of the first and second memory transistors; and a second erase voltage application operation is performed without performing the erase verify operation on another of the first and second memory transistors.

Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.

Abstract: According to some embodiments, a memory system includes a memory device including a plurality of memory cells capable of storing a plurality of bit data corresponding to a plurality of levels, respectively, and a controller configured to read data from the memory device, perform an error correction when there is an error in the read data, and determine a variation in a level before and after error correction of the read data.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.

Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.

Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.

Abstract: A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.

Abstract: A voltage regulator includes an operational amplifier that compares a feedback voltage that is proportional to an output voltage and a predetermined reference voltage that corresponds to a desired output voltage. The operational amplifier controls the conduction state of an output transistor according to the comparison. A detecting circuit monitors the operating state of the operational amplifier, and in the case that the operational amplifier is not operating, outputs a signal which causes the output transistor to be placed in a non-conductive state.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.