Abstract: A semiconductor memory device includes a memory cell array with bit lines and word lines connected thereto. A first power supply circuit generates a selected bit line voltage. A second power supply circuit generates a non-selected bit line voltage. A third power supply circuit generates a selected word line voltage. A fourth power supply circuit generates a non-selected word line voltage. A first decoder connects the selected bit line to the first power supply circuit and connects the non-selected bit line to the second power supply circuit. A second decoder connects the selected word line to the third power supply circuit and connects the non-selected word line to the fourth power supply circuit. A capacitive element is between a first node that is between the second power supply circuit and the first decoder and a second node that is between the third power supply circuit and the second decoder.