Patents Assigned to Toshiba Shibaura Denki Kabushiki Kaisha
  • Patent number: 4586163
    Abstract: A data memory circuit is provided including a plurality of depletion type MOS transistors connected in series, each of which stores data including two bits in the form of a threshold voltage. One end of the memory circuit is kept at a power source level and the second terminal thereof is kept at a ground potential level. 0 V is applied to the gate electrode of one selected MOS transistor while the power source voltage is applied to the gate electrodes of the remaining MOS transistors. As a result, a voltage equal to an absolute value of the threshold voltage of the selected MOS transistor is produced at the second terminal. A converter converts the voltage produced at the second terminal into corresponding binary coded data.
    Type: Grant
    Filed: July 1, 1983
    Date of Patent: April 29, 1986
    Assignee: Toshiba Shibaura Denki Kabushiki Kaisha
    Inventor: Hideharu Koike
  • Patent number: 4502207
    Abstract: A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.
    Type: Grant
    Filed: December 16, 1983
    Date of Patent: March 5, 1985
    Assignee: Toshiba Shibaura Denki Kabushiki Kaisha
    Inventors: Jiro Ohshima, Masahiro Abe, Yutaka Koshino
  • Patent number: D276999
    Type: Grant
    Filed: May 27, 1982
    Date of Patent: January 1, 1985
    Assignee: Toshiba Shibaura Denki Kabushiki Kaisha
    Inventor: Takeshi Arimura