Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure.

Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.

Abstract: A white light emitting diode package structure having a silicon substrate is disclosed. The white light emitting diode package structure comprises a silicon substrate having a plurality of cup-structures thereon, one of a plurality of blue light emitting diodes is respectively disposed in each cup-structure, and a phosphor structure covering the silicon substrate and the cup-structures. The blue light emitting diodes have various wavelengths and the phosphor structure has a plurality of kinds of phosphor powders and a sealing material. Each kind of phosphor powder is able to convert blue light within a certain wavelength into yellow light.

Abstract: The present invention provides a method of fabricating a hinge. First, a wafer is provided, and a hinge region and at least two through regions are defined on the wafer. The wafer in the hinge region is partially removed from a bottom surface of the wafer. Subsequently, the wafer in the through regions is completely removed from a top surface of the wafer, and the hinge is formed. Thereafter, a wafer level test is performed on the hinge of the wafer. Next, an etching process is performed to adjust the shape of the hinge. According to the method of the present invention, the thickness of the hinge is no longer limited by the thickness of the wafer, and the hinge can accept the wafer level test.

Abstract: A cutting method for wafer-level packaging capable of protecting the contact pad, in which several cavities and precutting lines are formed at the front surface of a cap wafer, and the depth of each precutting line is lesser than the thickness of the cap wafer, followed by the bonding of the cap wafer to the device wafer, which has several devices and several bonding pads disposed on the surface of the device wafer, followed by performing a wafer dicing process, along the precutting lines cutting through the cap wafer, and after removing a portion of the cap wafer that is not bonded to the device wafer, for exposing the bonding pads at the surface of the device wafer, and finally performing a dicing process for forming many packaged dies.

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract: A method of fabricating a diaphragm of a capacitive microphone device is provided. First, a substrate is provided, and a dielectric layer is formed on a first surface of the substrate. Than, a plurality of silicon spacers are formed on a surface of the dielectric layer, and the dielectric layer is patterned to form a plurality of dielectric bumps. Subsequently, a diaphragm layer is formed on a surface of the silicon spacers, a surface of the dielectric bumps, and the first surface of the substrate so that the diaphragm layer has a corrugate structure by virtue of the dielectric bumps. Thereafter, a planarization layer is formed on the diaphragm layer, and a second surface of the substrate is etched to form a plurality of openings corresponding to the corrugate structure. Following that, the dielectric bumps exposed through the openings are removed, and the planarization layer is removed.

Abstract: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.

Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

Abstract: A micro sample heating apparatus has a substrate, a micro heating device disposed on a first surface of the substrate, a cavity having a vertical sidewall and corresponding to the micro heating device positioned in a second surface of the substrate, and an isolation structure positioned on the second surface of the substrate. The isolation structure has an opening corresponding to the cavity, and the cavity and the opening form a sample room.

Abstract: A method of fabricating a suspended structure. First, a substrate including a photoresist layer hardened by heat is provided. Subsequently, the hardened photoresist layer is etched so as to turn the photoresist layer into a predetermined edge profile. Thereafter, a structure layer is formed on parts of the substrate and parts of the photoresist layer. Next, a dry etching process is performed so as to remove the photoresist layer, and to turn the structure layer into a suspended structure.

Abstract: A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of the plate corresponding to the through holes is not in contact with the glass wafer. A voltage source is provided, and two electrodes thereof respectively have electrical connections to the wafer and the plate. The wafer and the glass wafer are bonded to each other by the anodic bonding method so that a plurality of optical device caps are formed.

Abstract: A method for reducing dimension of an MEMS device. A single crystalline substrate having a diaphragm is provided. A first-step anisotropic dry etching process is performed to form an opening corresponding to the diaphragm in the back surface, the anisotropic dry etching stopping on a specific lattice plane extending from the edge of the diaphragm. A second-step anisotropic wet etching process is performed to etch the single crystalline substrate along the specific lattice plane until the diaphragm is exposed to form a cavity having a diamond-like shape.

Abstract: A cap wafer with patterned film formed thereon is etched through areas not covered by the patterned film to form a plurality of openings. Then, the cap wafer is bonded to a transparent wafer, and the cap wafer around the pattern film is segmented to form a plurality of cap structures. A device wafer with a plurality of devices and a plurality of contact pads electrically connected to the devices is subsequently provided. The cap structures and the device wafer are hermetically sealed to form a plurality of hermetic windows on the devices.

Abstract: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure.

Abstract: A wafer carrier for carrying a wafer includes a transparent base and a conducting layer. The transparent base has dimensions similar to that of the wafer, and bonds the wafer with a bonding layer. The conducting layer is transparent, and can be attracted by an electrostatic chuck so that the electrostatic chuck can deliver the wafer.

Abstract: A packaging wafer has a plurality of cavities and a plurality of trenches on a front surface thereof. The packaging wafer is bonded to the element wafer, and a first cutting method is performed. Afterward a piece of tape is provided and is attached to the packaging wafer. Moreover, a second cutting process is performed and then the piece of tape is removed. Therefore, a wafer level package is formed. In addition, the wafer level package is divided into a plurality of individual packages.

Abstract: A method of forming a suspended structure is disclosed. Initially, a substrate is provided. A patterned first sacrificial layer and a patterned second sacrificial layer are formed on a front surface of the substrate. The second sacrificial layer has an opening exposing a part of the substrate and a part of the first sacrificial layer. A structural layer is formed covering the abovementioned sacrificial layers. Thereafter, a lift-off process is performed to remove the second sacrificial layer and define the pattern of the structural layer. A first etching process is performed on a back surface of the substrate utilizing the first sacrificial layer as an etching barrier and a through hole is formed under the first sacrificial layer. A second etching layer is performed to remove the first sacrificial layer and a suspended structure is thereby formed.

Abstract: A substrate is provided and a plurality of trenches are formed in the front surface of the substrate. Then, a thermal oxide layer is formed on inner walls of the trenches and the front surface of the substrate. Subsequently, a first structural layer is formed on the thermal oxide layer, dopants are implanted into the first structural layer, a second structural layer is formed on the first structural layer, and an annealing process is performed to reduce the stress of the first and second structural layers. Following that, the first and second structural layers are patterned to form diaphragms. Finally, the second structural layer is mounted on a support wafer with a bonding layer, and the back surface of the substrate is etched by deep etching techniques to form back chambers corresponding to the diaphragms. Each back chamber has a vertical sidewall and partially exposes the first structural layer.