Abstract: An adaptive current limiter including a conversion network and an amplifier network developing an adaptive current limit signal for use by a switching regulator to limit peak current through an inductor of the switching regulator. The switching regulator develops a pulse control signal for controlling switching of current through the inductor to convert an input voltage to an output voltage. The conversion network provides a limit value by applying a duty cycle of the pulse control signal to a reference value. The amplifier network is configured to develop the adaptive current limit signal based on the limit value. The conversion network may multiply the reference value by the duty cycle to develop the limit value. The amplifier network may include a current source providing a fixed reference current to an amplifier to establish a minimum level of the adaptive current limit signal.

Abstract: A switched capacitor voltage reference including a single bias current source, three capacitors, diode devices, an amplifier and switching circuits for developing a temperature independent reference voltage. A single current source avoids having to match multiple current sources. A first capacitor and at least one diode device set a voltage having a negative temperature coefficient. A second capacitor and each of the diode devices set a voltage having a positive temperature coefficient. A third capacitor allows adjustable gain to enable a wide voltage range including a low voltage such as less than one volt. The switching circuits switch between multiple modes for developing and then combining the different temperature coefficient voltages. The topology allows a simple amplifier to be used. The topology is inherently accurate and does not require device trimming. An averaging method may be used to compensate for any mismatch between the diode devices.

Abstract: A clock generator with comparator error compensation includes an amplifier which develops an error voltage based on a difference between a sample voltage of a charge voltage and a predetermined reference voltage. The charge voltage develops a clock signal, such as a sawtooth waveform. A comparator compares the charge voltage with the error voltage to develop a compare signal. A sample and discharge control network is operative to develop the sample voltage in response to the compare signal, and then to switch between charging and discharging of the charge voltage. The amplifier develops the error voltage to ensure that the charge voltage switches at a level of the reference voltage to eliminate comparator errors, such as switching delay or input offset voltage. A second comparator and another amplifier may be provided to control switching in both directions, such as for developing a triangular waveform or the like.

Abstract: A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first and second transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first, third and fifth transistors are series-coupled between voltage supply lines forming a first current path, and the second and fourth transistors are series-coupled between the supply lines forming a second current path. The control terminals of the first and second transistors are coupled together and the control terminals of the third and fourth transistors are coupled together. The bias network biases the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain constant current level through the first and second current paths independent of voltage variations of the supply lines and at very low supply voltage.

Abstract: A fully differential amplifier with automatic offset voltage zeroing including first and second dynamically switched current mirrors and an output circuit. Each current mirror toggles operation between an autozeroing phase in which it mirrors a first current level indicative of a level of a first input terminal to provide a mirrored current, and an output phase in which it applies a difference current to a common output node. The difference current is a difference between the mirrored current and a second current level indicative of a level of a second input terminal. The first and second dynamically switched current mirrors operate out of phase with respect to each other during respective periods of each cycle of a clock signal. The output circuit develops first and second output signals on first and second output terminals at first and second polarities, respectively, based on a level of the common output node.

Abstract: A fully differential amplifier with automatic offset voltage zeroing including first and second dynamically switched current mirrors and an output circuit. Each dynamically switched current mirror toggles operation between an autozeroing phase in which it mirrors a first current level indicative of a level of a first input terminal to provide a mirrored current, and an output phase in which it applies a difference current to a common output node. The difference current is a difference between the mirrored current and a second current level indicative of a level of a second input terminal. The first and second dynamically switched current mirrors operate out of phase with respect to each other during respective periods of each cycle of a clock signal. The output circuit develops first and second output signals on first and second output terminals at first and second polarities, respectively, based on a level of the common output node.

Abstract: A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first and second transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first, third and fifth transistors are series-coupled between voltage supply lines forming a first current path, and the second and fourth transistors are series-coupled between the supply lines forming a second current path. The control terminals of the first and second transistors are coupled together and the control terminals of the third and fourth transistors are coupled together. The bias network biases the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain constant current level through the first and second current paths independent of voltage variations of the supply lines and at very low supply voltage.