Abstract: An imaging device according to one aspect of the present disclosure includes: a semiconductor substrate; and pixels. Each of the pixels includes: a photoelectric converter that converts incident light into electric charge; a diffusion region provided in the semiconductor substrate and electrically connected to the photoelectric converter; a first transistor including a gate, and the diffusion region as one of a source and a drain; and a plug that is directly connected to the diffusion region, is electrically connected to the photoelectric converter, and includes a semiconductor. The height of the plug and the height of the gate from the surface of the semiconductor substrate are equal to each other.

Abstract: A solid state imaging device has a global shutter structure and includes: a photodetector; a wiring layer; a first transparent insulating film disposed immediately above the photodetector and penetrating the wiring layer; a transparent protective film covering the wiring layer and the first transparent insulating film, and having a higher refractive index than the first transparent insulating film; a first projection provided on the transparent protective film and having a quadrilateral shape in top view; and a second transparent insulating film having a lower refractive index than the first projection.

Abstract: In a solid state imaging device having a plurality of pixels arranged in a matrix on a substrate, each of the plurality of pixels includes a photoelectric conversion region and an element separation region separating the photoelectric conversion region. The substrate includes a semiconductor substrate, a first epitaxial layer formed on the semiconductor substrate, and a second epitaxial layer formed on the first epitaxial layer. The photoelectric conversion region and the element separation region are formed over the first epitaxial layer and the second epitaxial layer.

Abstract: A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.

Abstract: A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.