Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: Accessing of adjacent arrays of memory in a semiconductor integrated circuit is facilitated by numbering the arrays of memory in accordance with a digital Gray code in which the addresses of adjacent arrays differ in only one digit. Each array is selected by the full array select address field. Each sense amplifier and I/O circuitry between memory arrays and shared by two adjacent memory arrays is selected by the full array select address field less one bit, that bit being the single address bit that differs between the addresses of the two adjacent Grey code numbered memory arrays. This permits faster decoding and enabling of the sense amplifier and I/O signal circuitry.

Abstract: A low power digital to analog converter (DAC) circuit is presented that is particularly suited for liquid-crystal display driver systems. The DAC according to one embodiment of the present invention uses a dedicated resistive divider chain that is selectively switched between adjacent pairs of coarse analog reference signals to generate finer analog reference signals. In a preferred embodiment, the resistance of the switches are used in combination with the resistive divider chain to form a voltage divider. In the preferred embodiment, the DAC of the present invention uses MOS transistors to implement the switches and the resistive elements in the divider chain.

Abstract: A circuit technique that optimizes the activation timing of a dynamic sense amplifier includes a circuit that closely tracks process variations to generate the optimum activation signal for the dynamic sense amplifier. In another embodiment, the activation timing for the dynamic sense amplifier is made programmable on a chip-by-chip basis to not only arrive at the optimal timing for the activation signal, but to also enable the manufacturer to guarantee a certain amount of margin in the operation of the circuit.

Abstract: A digital system includes apparatus for propagating falling and rising edges of a digital signal through two separate data paths each optimized to maximize propagation of one edge of the signal. The first data path is structured to propagate the first transition (e.g., falling edge) of the digital signal with a delay less than that experienced by the second transition (rising edge); and the second data path is structured to propagate the second transition with much less delay than that experienced by the first data transitions. The outputs of the two data paths are applied to a combining circuit, and put together to form a final representation of the digital signal to use the first and second state transitions as propagated by the apparatus.

Abstract: A method and apparatus for renumbering memory arrays may be used in memory systems having a target memory capacity formed from a number (N) of memory arrays. Upon powerup of the memory system, if a portion (M) of the N memory arrays are identified as defective, the memory arrays are renumbered from 0 to (N-M) to provide a logically continuous memory system having a smaller memory capacity than the target memory capacity.

Abstract: A memory device according to the invention includes at least first and second memory arrays having a number of word lines. Each of the word lines are coupled to a shared word line bootstrap circuit so that every word line from the first array shares a bootstrap circuit with a word line from the second array.

Abstract: A circuit and a method for limiting current during block write operations in memory integrated circuits such as graphics or video RAMs. A bias line for all sense amplifiers located between two memory sub-arrays is divided into independent segments connected to groups of sense amplifiers. Each segment is biased by a separate sense amplifier enable transistor. With much reduced loading, each enable transistor connected to a segmented bias line is significantly smaller in size. Thus, the sense amplifier crowbar or switching current is significantly reduced when writing a block of data of opposite polarity into a block of memory cells.

Abstract: An improved method and circuit for a word line driver in memory integrated circuits is disclosed. Instead of connecting the gate terminal of an isolation transistor to a constant high power supply voltage, the present invention momentarily boosts the voltage at the gate terminal to allow for a full logic high voltage to be transferred to the gate terminal of a word line driver transistor. Then the voltage at the gate terminal of the isolation transistor is reduced to its original level before the signal at the drain terminal of the word line driver transistor is boosted from ground to voltages above the power supply level. Thus, a maximized boosted voltage is trapped at the gate terminal of the word line driver transistor to improve the drive capability of the word line driver transistor.

Abstract: A CMOS input buffer is described for such CMOS circuits as dynamic random access memories, microprocessors, and the like, for receiving TTL logic high and low level signals. The input buffer includes an input stage formed from a p-channel and n-channel MOS transistors configured to have substantially equal transconductances, connected to form a series current path between a bias voltage and a lower voltage (e.g., ground), setting the trip point of the input stage approximately midway between the typically specified TTL logic high and low levels. The differential between the bias and lower voltages from which the input buffer operates assures that at least one of the MOS transistors is off for a TTL logic high or low level input, obviating power consumption while the input signal is at such level. The input buffer is also made insensitive to symmetrical power supply noise, consumes less power, and is made insensitive to threshold voltage variations.

Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.

Abstract: A memory circuit with programmable memory array organization and number of data output terminals, capable of connecting unused output buffers in parallel in organizations requiring fewer output terminals than the maximum possible. Parallel connection of output buffers improves output transient performance and employs otherwise dfsabled output buffers to reduce waste of silicon area.