Abstract: A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not require disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories.

Abstract: A method and a circuit for fast equilibration of complementary data lines in memory circuit following a write cycle. The circuit of the present invention separately controls the on/off timing of pull-up and pull-down transistors coupled to the data lines to obtain faster equilibration. In one embodiment incorporating an equilibration transistor between the data lines, the pull-up transistor coupled to the high data line is momentarily turned off after a write cycle, to allow the voltage on the high data line to drop all the way down to the voltage on the recovering low data line to reduce equilibration delay.

Abstract: A method and a circuit for fast equilibration of complementary data lines in memory circuit following a write cycle. The circuit of the present invention separately controls the on/off timing of pull-up and pull-down transistors coupled to the data lines to obtain faster equilibration. In one embodiment incorporating an equilibration transistor between the data lines, the pull-up transistor coupled to the high data line is momentarily turned off after a write cycle, to allow the voltage on the high data line to drop all the way down to the voltage on the recovering low data line to reduce equilibration delay.