Abstract: A parallel bus alarm system in which address signals are represented by successive voltage steps, and responses are represented by current increments. Each alarm element, in response to its addressing, controls a variable current increment to flow in the bus, the magnitude of the current increment being a function of an associated analog measurement to be reported. Each alarm element also causes a predetermined current increment to flow in the bus in response to a condition arising which requires reporting, the total current change thus being directly proportional to the number of alarm indications.

Abstract: A single-wire loop alarm system in which an identification module is placed across each alarm switch. Any module which is across an open switch is powered by the loop current and, in response to a pulse count in the loop representing its address, changes the loop impedance in order to report on its status. The loop current may alternate in direction so that oppositely poled modules may be used, thus allowing a larger number of powered modules to accommodated at the same time.

Abstract: A single-wire loop alarm system in which the status of each alarm switch can be determined and which is relatively immune to the effects of noise. False alarms are avoided by incorporating an integrator in the loop potential test circuit; during polling, however, the integrator is switched out. Low-frequency noise is discriminated against by verifying the existence of an alarm condition; the loop current is doubled and, if the alarm condition is being caused by an impedance-introducing open alarm switch, the loop voltage change should double. Polling is made more reliable by relying on a "window" test, rather than a simple threshold test.