Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: The invention relates to the collective fabrication of superposed microstructures, such as an integrated circuit and a protective cover. Individual structures each comprising superposed first and second elements are fabricated collectively. The first elements (for example, integrated circuit chips) are prepared on a first plate and the second elements (for example, transparent covers) are prepared on a second plate. The plates are bonded to each other over the major portion of their facing surfaces, but with no bonding of the defined zones in which there is no adhesion. The individual structures are then diced via the top on the one hand and via the bottom on the other hand along different parallel dicing lines passing through the zones with no adhesion, so that, after dicing, the first elements retain surface portions (those lying between the parallel dicing lines) that are not covered by a second element. A connection pad may thus remain accessible at this point.

Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: Process for fabricating a structure in the form of a wafer, including at least a substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, the process including: forming, on a substrate, at least one intermediate layer including at least one base material in which extrinsic atoms or molecules are distributed, these differing from the atoms or molecules of the base material, so as to constitute a substructure; applying a base heat treatment to this substructure such that, in the temperature range of this heat treatment, the presence of the chosen extrinsic atoms or molecules in the chosen base material causes a structural transformation of said intermediate layer; and joining a superstrate to said heat-treated intermediate layer so as to obtain said structure in the form of a wafer.

Abstract: The invention relates to the collective fabrication of superposed microstructures, such as an integrated circuit and a protective cover. Individual structures each comprising superposed first and second elements are fabricated collectively. The first elements (for example, integrated circuit chips) are prepared on a first plate and the second elements (for example, transparent covers) are prepared on a second plate. The plates are bonded to each other over the major portion of their facing surfaces, but with no bonding of the defined zones in which there is no adhesion. The individual structures are then diced via the top on the one hand and via the bottom on the other hand along different parallel dicing lines passing through the zones with no adhesion, so that, after dicing, the first elements retain surface portions (those lying between the parallel dicing lines) that are not covered by a second element. A connection pad may thus remain accessible at this point.

Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Abstract: The invention relates to a method for producing a semi-conductor structure consisting in a) producing at least one part of a circuit in or on a surface layer (2) of a substrate, which comprises said surface layer (2), a layer (4) buried under said surface layer and an underlying layer (6) used in the form of a first support, b) transferring said substrate to a handle substrate (20) and in removing the first support (6), c) forming a bonding layer (12) on said electrically conductive or a grounding plane forming layer (14) and e) transferring the assembly to a second support (30) and in removing the handle substrate (20).

Abstract: The invention relates to a process for making a semiconducting structure composed of a surface layer (2), at least one buried layer (4) and a support, comprising: —a first step to make a first layer (44) made of a first material on a first support, and at least one area (26, 28) in this first layer made of a second material with an etching rate greater than the etching rate of the first material, —a second step for the formation of the surface layer (2), by assembly of the structure on a second support, and thinning of at least one of the two supports.

Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: A method for assembling a first and a second wafer of material, including routing at least the first wafer and assembling the first and second wafer.