Abstract: A probe card is disclosed. The probe card includes a first disc, a second disc, an alignment plate and multiple micro probes. One of the micro probes includes a linear segment and a curved segment connected to each other at an angle stop. The first disc includes a recessed area having multiple holes formed therein, wherein one of the holes is configured to receive the linear segment of the micro probe. The second disc includes a recessed area having multiple holes formed therein, wherein one of the holes is configured to receive the curved segment of the micro probe. Placed within the recessed area of the second disc, the alignment plate includes multiple holes formed therein, wherein one of the holes is configured to receive the curved segment of the micro probe.

Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with a full-wafer contactor disposed on the wafer. Some embodiments include placing a wafer on a chuck of the prober, aligning the wafer to a full-wafer contactor incorporated in the wafer prober, removably attaching the wafer to the full wafer contactor, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contactor that faces away from the wafer.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer test system includes an interposer having a first surface and a second surface facing away from the first surface. The system also includes a wafer translator having a first side facing the second surface of the interposer and a second side facing away from the first side and toward a wafer, the first side carrying a plurality of first terminals at a first scale and the second side carrying a plurality of second terminals at a second scale. The first scale is greater than the second scale.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober; removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

Abstract: Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies includes a wafer translator having a wafer-side facing the dies and an inquiry-side facing away from the wafer-side. The inquiry-side of the wafer translator carries a first and a second plurality of inquiry-side contact structures. The first plurality of the inquiry-side contact structures is interleaved with the second plurality of the inquiry-side contact structures.

Abstract: Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for adjusting a wafer translator for testing semiconductor dies includes the semiconductor wafer translator having a wafer translator substrate with a wafer-side configured to face the dies. A plurality of wafer-side contact structures is carried by the wafer-side of the wafer translator. The apparatus also includes a shaping wafer having a shaping wafer substrate, and a plurality of cavities in the shaping wafer substrate. The wafer-side contact structures are shaped by contacting surfaces of the cavities of the shaping wafer substrate.

Abstract: Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies includes a semiconductor wafer translator having a wafer-side positioned to face toward a device under test, and an inquiry-side facing away from the wafer-side. The apparatus also includes a flexible arm peripherally connected to the wafer translator, and an evacuation opening within the flexible arm or within the wafer translator. The evacuation opening is open to a flow of a gas in a first position of the flexible arm, and closed to a flow of the gas in a second position of the flexible arm.

Abstract: Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies on a wafer includes a wafer translator having a wafer-side facing toward the wafer, and an inquiry-side facing away from the wafer-side. The wafer has an active side facing the translator. The apparatus includes a peripheral seal configured to seal a space between the wafer translator and the wafer, and a valve in a fluidic communication with the space between the wafer translator and the wafer.

Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

Abstract: Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces.

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate.