Abstract: The present invention is directed to an apparatus for cooling communication equipment using a heat pipe, which releases heat from a heat-emitting unit by a simple, reliable and safe scheme. The present invention provides an apparatus for releasing heat, which comprises: a heat pipe for transferring heat generated in a heat-emitting unit of the communication equipment and being mounted on a predetermined location of the heat-emitting unit; a vaporizing unit for vaporizing liquid with the heat transferred via the heat pipe and draining the vaporized liquid through a vaporization line, wherein a lower part of the vaporizing unit contacts a predetermined location of the heat pipe; a condensing unit for performing heat-exchange by condensing the vaporized liquid from the vaporizing unit and returning the condensed liquid to the vaporizing unit through a condensation line; and a small capacity fan for releasing air to the outside when the condensing unit performs the heat-exchange.

Abstract: A method optimizes a DSP Input clock using a clock comparing/analyzing circuit. The method of the present invention enables PLD to select a delay function of the PLD and signals from a plurality of patterns, in addition to varying three elements' values of R, L and C, a driver delay, and a characteristic change by peripheral elements of patterns that a clock passes to thereby obtain an optimal characteristic. Particularly, the inventive method provides an optimal clock with the best performance among clocks from the pattern.

Abstract: The present invention relates to an apparatus for generating clock pulses using a Direct Digital Synthesizer (DDS). The present invention seeks to solve the problems of the conventional clock generator using a Phase Locked Loop (PLL) circuit where the output clock frequency cannot be varied and the output clock signal is degraded because of jitter and phase noise. The claimed apparatus comprises a phase accumulator, a phase-to-magnitude converter, a Digital-to-Analog (DA) converter, a band pass filter, and a comparator, which are serially connected. A 10×PLL multiplier provides a 196.608 MHz clock signal to the phase accumulator, the phase-magnitude converter and the digital analog converter, respectively. The phase accumulator also receives a Frequency Tuning Word (FTW) and using this FTW and the 196.608 MHz clock, outputs a desired specific frequency value.