Abstract: Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface.

Abstract: A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract: A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

Abstract: A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.

Abstract: A multilevel inverter includes a first half bridge in series with a second half bridge, each comprising a switch having a channel. The switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch. The inverter may also include a third half bridge. The inverter can be configured such that in operation, switches of the third half bridge are switched at a substantially lower frequency than the switches of the first and second half bridges.

Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Abstract: A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.