Abstract: Setting a polishing rate and a polishing time in chemical mechanical polishing can be performed with high accuracy by considering a product wafer of an object to be polished, and an instrumental error between apparatuses to be used, etc. By using, as a calculating formula, a formula well approximating a portion of a curve representing a state of chemical mechanical polishing on a side showing a target polishing amount, the polishing rate and the polishing time can be set with high accuracy according to a state of chemical mechanical polishing for actually polishing a product wafer. In the calculating formula, a parameter “A” relating to a film property of a film of an object to be polished, a parameter “B” relating to a roughness state of a film surface, and a parameter “C” relating to an instrumental error differential between apparatuses of a chemical mechanical polishing apparatus are joined by operators.

Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

Abstract: A technique capable of preventing breakage of a semiconductor wafer in a single-wafer RTP apparatus is provided. Open-loop control is made in a temperature rising process, in which the temperature of the semiconductor wafer is 500° C. or lower, and a revolution speed of the semiconductor wafer is relatively reduced to 100 rpm or lower even if the bowing of the semiconductor wafer occurs. Therefore, a centrifugal force exerted on the semiconductor wafer is reduced, whereby it becomes possible to prevent the semiconductor wafer from dropping from a stage of the single-wafer RTP apparatus. Additionally, closed-loop control is made in the temperature rising process, in which the temperature of the semiconductor wafer is higher than 500° C., and in a main treatment process, and further the revolution speed of the semiconductor wafer is relatively increased. By so doing, the almost uniform in-plane temperature of the semiconductor wafer can be achieved and the bowing of the semiconductor wafer can be prevented.

Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

Abstract: In a semiconductor device manufacturing process using a low-dielectric-constant insulation film as an interlayer insulation film, a stress exerted on wiring layers and interlayer insulation films is reduced. In a semiconductor device in which a plurality of buried wiring layers are formed in the interlayer insulation films each formed of a low-dielectric-constant insulation film lower in mechanical strength than a silicone oxide film formed by, for example, a CVD method, a first layer of wiring, on a lower layer of which a low-dielectric-constant insulation film is not disposed, serves as a bonding pad, and bump electrodes are formed on the wiring so as to become higher than a position where the uppermost buried wiring is formed.

Abstract: A FOUP having semiconductor wafers received therein is transferred to a loading port and then the door of the FOUP is fixed and removed by a FIMS door and then the semiconductor wafers are taken out of the shell of the FOUP and then a predetermined manufacturing processing is performed to the semiconductor wafers. After performing the manufacturing processing, the semiconductor wafers are returned into the shell and the FIMS door is returned to a closed position and the shell is retracted about 50 mm to 65 mm to form a gap between the FIMS door and the shell. Then, purge gas is introduced from a gas introduction pipe arranged above the loading port on the left and right sides in a slanting forward direction of the FIMS door into the shell to replace the atmosphere in the shell with the purge gas.

Abstract: A manufacturing method of semiconductor device capable of suppressing or preventing formation of a dissolution region of composition atoms such as a pit in a semiconductor wafer. After oxide film on a semiconductor wafer is removed by dipping plural pieces of the semiconductor wafer accommodated in a carrier into chemical liquid containing fluoro acid, chemical liquid adhering to the semiconductor wafer is washed out of the semiconductor wafer by rinse processing using de-ionized water. At least in the rinse processing of this wet processing, light is projected to the semiconductor wafer from a light source provided on a wet etching apparatus. Adjusting electromotive force caused by battery reaction at a pn junction of the semiconductor wafer by adjusting the state of the light L enables generation of a pit in the semiconductor wafer.

Abstract: This invention provides a solid-state imaging device which enables its cell area to be reduced while maintaining a light receiving area. First, a plurality of isolation areas are formed in a semiconductor substrate. Then, p-type well is formed by implanting p-type impurity into the interior organization of an active area surrounded by the isolation areas. Next, by using ion implantation method, a charge accumulating area, which is a n-type semiconductor area, is formed deep in the p-type well. Consequently, photo diode is formed in a deep portion apart from the surface of the semiconductor substrate. After that, an electric transferring MIS transistor is formed above and apart from the charge accumulating area, so that the photo diode and the MIS transistor are formed in a vertical structure.

Abstract: A semiconductor manufacturing apparatus comprising an integrated measuring instrument for measuring the form or size of the element to be formed into a wafer, an etching unit for etching the wafer by making use of plasma generated under reduced pressure, an ashing unit for ashing the etched wafer, a wetting unit for wetting the etched wafer, a drying unit for drying the wafer which has gone through the wetting treatment, a transport means whereby the wafers housed in a wafer cassette are transported one by one successively to said metrology and each treating unit, and a transport chamber provided with a wafer cassette inlet for receiving a cassette containing sheets of wafer to be etched, in which said metrology, etching unit, ashing unit, wetting unit, drying unit and transport means are connected by a depressurizable transport passage.

Abstract: In a semiconductor device manufacturing process using a low-dielectric-constant insulation film as an interlayer insulation film, a stress exerted on wiring layers and interlayer insulation films is reduced. In a semiconductor device in which a plurality of buried wiring layers are formed in the interlayer insulation films each formed of a low- dielectric-constant insulation film lower in mechanical strength than a silicone oxide film formed by, for example, a CVD method, a first layer of wiring, on a lower layer of which a low-dielectric-constant insulation film is not disposed, serves as a bonding pad, and bump electrodes are formed on the wiring so as to become higher than a position where the uppermost buried wiring is formed.

Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

Abstract: By-products inside a furnace body of a CVD film forming apparatus after gas cleaning is performed in the furnace body are provided from being generated. The gas cleaning is performed in the furnace body by a plasma of a gas containing a halogen system gas and an Ar gas in an atmosphere in which the temperature of a heater disposed in the furnace body is approximately 500° C. or lower. Thereafter, a rise of the temperature of the heater is started. While the temperature of the heater is maintained constant, a film forming gas is introduced into the furnace body during a time period before the raised temperature reaches a temperature at which radicals or ions of a halogen system element are activated.

Abstract: In a semiconductor manufacturing process such as the CMP process with the large ratio of manual work, the automation is promoted in order to achieve the rationalization and the manpower reduction, the improvement of the processing ability, the reduction of the investment amount, and the improvement of the indirect operation efficiency. By just downloading the process recipe of the product wafer from the host computer to the CMP apparatus in the CMP process, the dummy wafer is processed under the predetermined process condition before processing the product wafer. In this manner, the unmanned operation can be achieved. In addition, the measurement data of the film thickness measuring device mounted to the unmanned CMP apparatus is transmitted together with such process data as the polishing time from the CMP apparatus to the host computer.

Abstract: Shortening TAT for processing express lots without reducing the utilization rate of manufacturing apparatuses for semiconductor device. When the number of vacant ports LPOT of a manufacturing apparatus EQ3 used in a next step is only one at the of time of completing a process for a normal lot LA by a manufacturing apparatus EQ1 and when there is a possibility that processes for an express lot LB performed by a manufacturing apparatus EQ2 will be completed before a remaining processing time period for a lot LC performed by the manufacturing apparatus EQ3 reaches a predetermined set value, the lot LA is transferred to a lot stocker LS for securing a vacant port LPOT and as soon as the processes for the express lot LB performed by the manufacturing apparatus EQ2 are completed, the express lot LB is transferred to the vacant port LPOT in the manufacturing apparatus EQ3.