Patents Assigned to Trellisware Technologies, Inc.
  • Patent number: 7698624
    Abstract: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 13, 2010
    Assignee: TrellisWare Technologies, Inc.
    Inventor: Georgios D. Dimou
  • Patent number: 7673213
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: March 2, 2010
    Assignee: Trellisware Technologies, Inc.
    Inventors: Keith Michael Chugg, Paul Kingsley Gray
  • Publication number: 20090313528
    Abstract: A method and system are provided in a wireless communications system comprising a plurality of nodes (users) working cooperatively. The system provides cooperative diversity by allowing nodes to actively share their antennas and other resources to obtain spatial diversity. The nodes receive the same message (information data) from a common source. Each node enhances the reliability of the message with a modern forward error correction (FEC) code, converts the FEC encoded message into an ensemble of symbols, divides the ensemble of symbols into packets, modulates, dithers and transmits the packets to a receiving node. The dithering process is performed by varying the signal amplitude, phase, frequency and/or symbol timing of the modulated packets. A unique dither pattern is assigned to each node. The receiving node captures a composite signal comprising the transmitted packets of all or most of the transmitting nodes in the cooperative communications system.
    Type: Application
    Filed: October 6, 2008
    Publication date: December 17, 2009
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Keith M. Chugg, Mark Johnson
  • Patent number: 7584400
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: September 1, 2009
    Assignee: TrellisWare Technologies, Inc.
    Inventors: Paul Kingsley Gray, Keith Michael Chugg
  • Publication number: 20080107044
    Abstract: Systems and methods are presented for conducting a relayed communication involving a source node, a plurality of intermediate nodes, and at least one destination node, involving at the source node transmitting a signal associated with the relayed communication on a first medium allocation, at each one of the plurality of intermediate nodes relaying the signal onto a next medium allocation in response to receiving the signal as transmitted on at least one medium allocation up to a current medium allocation, and at the at least one destination node receiving the signal as transmitted on at least one medium allocation up to a last medium allocation, wherein at least one node among the plurality of intermediate nodes and the at least one destination node receives signals associated with the relayed communication from multiple intermediate nodes as transmitted on at least one medium allocation.
    Type: Application
    Filed: August 2, 2007
    Publication date: May 8, 2008
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Adam M. Blair, Thomas A. Brown, Mark L. Johnson
  • Publication number: 20080098279
    Abstract: Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 24, 2008
    Applicant: TrellisWare Technologies, Inc.
    Inventor: Georgios D. Dimou
  • Publication number: 20080098281
    Abstract: SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 24, 2008
    Applicant: TrellisWare Technologies, Inc.
    Inventor: Georgios D. Dimou
  • Publication number: 20070234187
    Abstract: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Applicant: TrellisWare Technologies, Inc.
    Inventor: Georgios Dimou
  • Publication number: 20070011566
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.
    Type: Application
    Filed: April 14, 2006
    Publication date: January 11, 2007
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Paul Gray, Keith Chugg
  • Patent number: 7096412
    Abstract: In a digital information processing system wherein a model of a finite state machine (FSM) receiving a plurality of FSM inputs and producing a plurality of FSM outputs is represented by a reduced-state trellis and wherein the FSM inputs are defined on a base closed set of symbols, a novel method is presented for updating soft decision information on the FSM inputs into higher confidence information whereby (1) the soft decision information is inputted in a first index set, (2) a forward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce forward state metrics, (3) a backward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce backward state metrics, wherein the backward recursion is independent of the forward recursion and (4) the forward state metrics and the backward state metrics are operated on to produce the higher confidence information.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: August 22, 2006
    Assignee: TrellisWare Technologies, Inc.
    Inventors: Xiaopeng Chen, Keith M. Chugg
  • Patent number: 7010069
    Abstract: A method for co-channel interference identification and mitigation employs adaptive sequence detection in connection with a model composed of a signal of interest and a combination of other signals which constitute interference in a channel of interest, wherein the signal of interest is distinguished from the interference by adaptive tracking of signal parameters of all identifiable signals. In a particular embodiment, the process involves estimating the number and time spans of co-channel interference channels based on maximum likelihood estimation and minimum description length from training information derived from a single time division multiple access packet; and then applying the estimate to mitigation of co-channel interference at a receiver. Per-survivor-processing is one technique for adaptive sequence detection.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: March 7, 2006
    Assignee: Trellisware Technologies, Inc.
    Inventors: Keith M. Chugg, Gent Paparisto, Prokopios Panagiotou
  • Publication number: 20060031737
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 9, 2006
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Keith Chugg, Paul Gray
  • Publication number: 20050216819
    Abstract: The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.
    Type: Application
    Filed: February 16, 2005
    Publication date: September 29, 2005
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Keith Chugg, Paul Gray, Georgios Dimou, Phunsak Thiennviboon
  • Patent number: 6614859
    Abstract: A method and a system are provided which uses vector per-survivor processing (PSP) on the outputs of an array of antennas of arbitrary geometry to jointly estimate angles of arrival of multipath components of the transmitted data sequence (i.e., the modulated data signal) while extracting an estimate of the modulated data. The system includes an antenna array of arbitrary geometry (i.e., arbitrary spacing between elements, directional, omnidirectional, etc.), each element of which has its output applied to a corresponding matched filter. The matched filter outputs in turn are sampled and applied to a vector-type PSP engine, wherein the vector PSP engine computes an estimate of the channels between the transmitter antenna and the receiver antenna elements to construct a channel estimation matrix. Angle of arrival estimates of each of the multipath components are extracted from the channel estimation matrix for the best survivor.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: September 2, 2003
    Assignee: TrellisWare Technologies, Inc.
    Inventor: Norman E. Lay