Abstract: A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received

Abstract: A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load.