Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
Type:
Grant
Filed:
April 1, 2005
Date of Patent:
November 11, 2008
Assignees:
Triad Semiconductor, Viasic, Inc.
Inventors:
James C. Kemerling, David Ihme, William D Cox