Abstract: A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.

Abstract: A binary voting solenoid arrangement 10 is provided which operates in a “2 out of 3” manner to provide relatively high safety, low spurious tripping and a relatively low installation cost, while also enabling on-line testing of each solenoid individually without process interruption. Solenoid arrangements 10, 10′ and 10″ are preferably used in a three-way configuration, while solenoid 10′″ may be used in a two-way configuration.

Abstract: A controller for executing an application program to process control information related to control elements includes one or more main processors that each run the application program; a time synchronization system that synchronizes the time clocks of the main processors; and a voting system that exchanges information between the main processors and compares the information received from the other main processors. In addition, the controller includes one or more rendezvous signals sent to and received by the main processors as well as a mechanism for updating the time clocks based on a clocking midpoint of all processor signals.

Abstract: A computer system for generating a cause effect matrix as a user interface to develop a control program based on the cause effect matrix and to compile and download the resulting program into a programmable controller. A cause effect matrix diagram is used to develop a function block diagram program which is a standard IEC 1131-3 language. The function block diagram is translated into structured text which is compiled into intermediate code. The intermediate code is translated into the native code for the micro-processor of the target control system, including but not necessarily limited to the Motorola processor MPC-860. The automation of a cause effect matrix diagram to generate a function block diagram permits additional capability by allowing functions for causes, intersections, and effects. Because special functions may be included, the results of a cause generate timing functions or other computations before initiating the effect.

Abstract: The programming of programmable controllers and other sequential computing devices is facilitated by automatically generating an order for evaluating function blocks in a function block diagram and by automatically detecting any errors in a function block diagram which would adversely affect the generation of a unique evaluation order, such as illegal cycles, disconnected subnetworks, and/or wired-OR connections. The nodes affected by the noted errors are graphically displayed to the user, who then may use a graphical interface to edit the network until all the noted errors have been corrected. A recursive procedure analogous to a topological sort may be used to automatically generate a unique evaluation order.

Abstract: A binary voting solenoid arrangement 10 is provided which operates in a "2 out of 3" manner to provide relatively high safety, low spurious tripping and a relatively low installation cost, while also enabling on-line testing of each solenoid individually without process interruption. Solenoid arrangement 10 is preferably manifolded (not shown), to facilitate maintenance on any detected failure, and to simplify installation and replacement.

Abstract: A majority-voted output circuit generates an output parameter which is the majority vote of its input parameters by series-parallel combination of four intermediate switches, each said switch being a Boolean function of the input parameters, and the circuit being arranged so that failure of any one switch does not affect the value of the output parameter. Alternate embodiments are provided which use "don't care" signals to allow the majority vote of less than the full complement of input parameters. The majority-voted output circuit is subjected to testing by stepped transitions of its input parameters (to test for failure of any of the four intermediate switches) and by forcing current flow through predetermined current paths (to test for failure of a particular electrical connection).