Abstract: A video processor comprises an instruction set of programmed operations for operating on video data. The instruction set has an instruction which corresponds to a programmed operation for performing a motion estimation calculation between pixel data in frames of video data. The programmed operation causes the processor to calculate a measure of motion estimation at each of a plurality of search locations within a search window. The processor comprises a plurality of calculation units (6), each of the units (6) being operable to perform a calculation, or partial calculation, at a different search location. The plurality of calculation units (6) perform the calculations, or partial calculations, in parallel. The measure of motion estimation calculation is one of: a sum of absolute difference (SAD) calculation; a mean square error (MSE) calculation, a mean absolute error (MAE) calculation.

Abstract: The present application relates to a method for frame rate conversion. The present application relates also to a system for frame rate conversion and a computer comprising said frame rate. In addition, the present application relates to a computer readable medium having a computer program for performing said method. The method comprises defining a first frame rate profile with a first frame rate, defining at least a second frame rate profile with a second frame rate, rendering video frames at the first frame rate profile, detecting the quality of the rendered video frames, and switching from the first frame rate profile to the second frame rate profile at least depending on the detected quality of the rendered video frames.

Abstract: Memory systems are disclosed which are comprised of a two or dual layer printed circuit board. Attached to the top layer of the dual layer printed circuit board are a memory chip and a memory controller with aligned, optimistic pin outs that optimized signal integrity layouts between certain high speed pins in a single layer. A set of high speed lines, including the data lines, that do not include any vias connect certain of the pins of the memory controller to certain of the pins of the memory chip. The high speed lines are covered by a sub-PCB that includes a copper lay that extends a ground or electrical plane above the top layer of the dual layer printed circuit board.

Abstract: An improved method and system for edge adaptive interpolation. The method uses a “9×2” window to detect the edge direction with post-processing to remove any artifacts due to the possible false edge detection, and a hierarchical scheme is employed to reduce the computation required. The method detects if there is edge existing along the current pixel. If there is no edge, then the edge detection output will be 90 degrees (the interpolation will be performed along the vertical direction). If an edge does exist, the method determines whether the edge direction falls within a first or second direction group. Once the edge direction is assigned to a particular group (e.g., 0–90 degrees or 90–180 degrees), the edge direction will be detected among five (5) possible directions. To further improve the edge detection precision, and also to remove the possibility of false edge direction detection, a post-processing technique may be applied to the edge direction signal.

Abstract: A method and system for edge-adaptive frame rate up-conversion are disclosed.

Abstract: A method and apparatus provide a user interface for control of a display device. A video signal is provided to a display device and a graphic image is displayed by the display device. The video signal may be provided to the display device by a host computer system coupled to the display device. Input to the host computer system is received by a user manipulating the graphic image via an input device. The host computer system responds to the input by communicating a command to the display device, the command for adjusting a parameter of the display device. The parameter may be selected from a group consisting of: brightness, contrast, horizontal orientation, horizontal size, vertical orientation, vertical size, tilt, pincushion, and color tint for the display. The command may be communicated via a data sequence sent to the display device by the host computer system. The data sequence may be encoded onto the video signal sent to the display device by the host computer system.

Abstract: A method for evaluating the depth of a pixel in a scene, the scene enclosed in a view volume, the scene to be rendered from a camera position, the view volume having a near and a far plane, includes calculating a depth value for a pixel in the scene, the depth value being generated by a depth function of view distance within the view volume from the camera position, and storing the depth value in a floating-point format, the floating-point format including a mantissa and exponent, where, as the distance of the pixel to the far plane decreases, the absolute magnitude of the depth value generated by the depth function approaches the minimum non-negative number representable by the floating-point format.

Abstract: A method for interpolating a pixel during the deinterlacing of a video signal, the video signal including at least two fields of interlaced scan lines, each scan line including a series of pixels having respective intensity values, includes generating a motion value representative of the motion between successive frames about the pixel, detecting an edge direction about the pixel, performing an edge adaptive interpolation at the pixel, using the detected edge direction, and performing a motion adaptive interpolation at the pixel, using the generated motion value.

Abstract: A controller card is provided that allows the processing and display of two types of graphics pixel data for display in two environments. The card contains a first graphics controller chip coupled to the video capture port of a second graphics controller chip. In a first mode the first chip may generate graphics pixel data for display in a first environment. The pixel data is stored in the memory of the second chip reserved for graphics pixel data and transmitted to a display device coupled to the second chip. In a second mode, the video capture port may be coupled to a video source so that data captured in the video port is stored in the memory of the chip reserved for video pixel data. The second chip may then process and output to the display device both video pixel data and a second type of graphics pixel data generated by the second chip and stored in the memory of the second chip reserved for graphics pixel data.

Abstract: Video information is simultaneously generated for presentation on multiple displays by a display system including a video memory having a plurality of addressable storage locations, each storage location providing for the storage of data representing a component of an independent displayable image and a video controller providing a plurality of output display control and data signals connectable to a respective plurality of video displays. The video controller accesses the video memory in a predetermined addressing pattern so as to access a sequence of the components corresponding to a plurality of the independent displayable images. The video controller, in turn, generates the plurality of output display control and data signals whereby the sequence of the components provided by way of each of the plurality of the output display control and data signals corresponds to a respective one of the independent displayable images.