Abstract: In order to create a noise elimination device for the detection of the vertical sync pulse in video signals, which has a very fast locking behavior and in which additional components can be integrated easily, which components can measure fundamental parameters of the underlying composite video signal, it is proposed that the device comprises a vertical pulse detector (12), which detects successive vertical sync pulses in the composite video signal and a VPLL (vertical phase locked loop), which comprises at least a phase detector (18) that produces a phase error, at least a loop filter (20), at least an oscillator (16) on which the output signal of the vertical pulse detector is present as an input signal and which oscillator produces a clock signal phase-synchronized with the input signal, whereas the oscillator (16) is a counter which counts with an approximately constant clock frequency, while the length of an oscillation period of the oscillator (16) is determined by the change in its count due to a correc

Abstract: The invention relates to a method and/or a device for determining a constellation from a plurality of possible constellations with a constellation identification device which is used to determine the constellation of the signal from a plurality of possible constellations. This is advantageously achieved when a converter is arranged to convert the signal into polar coordinates provided with a radial component, and to provide a radius as a radial component of the signal, wherein the constellation identification device is constructed so as to determine the constellation of the signal from the radius.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.

Abstract: A graphics pipeline (20) for rendering graphics receives texture data (22) and vertex data (23). The texture data (22) define rectangular texture maps (24), which are axis-aligned in texture space. The vertex data (23) describe output quadrilaterals (25) in screen space. A rasterizer (27) rasterizes the input rectangle (24) by determining which texels are inside the input rectangle (24). A mapper (28) maps the texels inside the input rectangle (24) onto the output quadrilaterals (25). The mapping is performed by calculating screen space output coordinates from the texture space grid coordinates of the texels. For the calculation an equation is used comprising at least one linear combination of the texture space grid coordinates of the texels inside the input rectangles (24) and at least one product of real powers of the texture space grid coordinates of the texels inside the input rectangles (24).

Abstract: The invention relates to the field of video compression and, more specifically, to a video encoding method applied to an input sequence of frames in which each frame is subdivided into blocks of arbitrary size. This method comprises, for at least a part of said blocks of the current frame, the steps of generating on a block basis motion-compensated frames, each one being obtained from each current original frame and a previous reconstructed frame, generating from said motion-compensated frames residual signals, using a so-called matching pursuit (MP) algorithm for decomposing each of said generated residual signals into coded dictionary functions called atoms, the other blocks of the current frame being processed by means of other coding techniques, and coding said atoms and the motion vectors determined during the motion compensation step, for generating an output coded bitstream.

Abstract: The invention relates to a method and a circuit arrangement for deciding a symbol upon the reception of a signal including or coupled with a quadrature signal pair, wherein the decision is made by means of an analysis of the metric of at least one reception point to at least one nominal point in a complex coordinate space, and the metric is analyzed in the non-Cartesian or not exclusively Cartesian complex coordinate space. The decision is made after the analysis, and during the decision process, a second most probable nominal point and a reliability of the decision are determined.

Abstract: The present application relates to a method for frame rate conversion. The present application relates also to a system for frame rate conversion and a computer comprising said frame rate. In addition, the present application relates to a computer readable medium having a computer program for performing said method. The method comprises defining a first frame rate profile with a first frame rate, defining at least a second frame rate profile with a second frame rate, rendering video frames at the first frame rate profile, detecting the quality of the rendered video frames, and switching from the first frame rate profile to the second frame rate profile at least depending on the detected quality of the rendered video frames.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: The invention relates to a method and an apparatus for increasing the resolution of a data sequence, such as for example a video data sequence. Between two data values of a given data sequence at least one intermediate value is interpolated by applying low-pass filtering and at least one first and one second high-pass filterings to data values of the data sequence, subjecting the filter values obtained by the high-pass filterings to rank-order filtering and combining the filter result so obtained with the filter result obtained by low-pass filtering.

Abstract: An audio processing system includes a speech detector that receives and processes an audio input signal to determine if the input signal includes components indicative of speech, and provides a control signal indicative of whether or not the audio input signal includes speech. A speech processing device receives the audio input signal and processes the audio input signal to improve its quality if the control signal indicates that the audio input signal includes speech.

Abstract: A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.

Abstract: An occlusion detector (200, 201, 203, 205, 207) for detecting occlusion areas (108, 110) in an image (100) comprises a motion vector selector (202) for selecting at least two motion vectors (118, 120) from a set of motion vectors. It further comprises a pixel value comparator (206) for calculating a first and a second pixel value difference between a particular value of a particular pixel (112) of the image (100) and a second value of a second pixel (116) and a third value of a third pixel (114), both of a further image (102). The occlusion detector (200, 201, 203, 205, 207) further comprises a decision unit (204) for deciding whether the particular pixel (112) belongs to one of the occlusion areas (108, 110) by checking whether the first and second pixel value differences are larger than a first predetermined threshold and a second predetermined threshold, respectively.

Abstract: The invention relates to interpolation of an image information value for a pixel of an interline. The method comprises selecting, from a number of image directions, to each of which a direction quality value is assigned, a direction of interpolation by comparing these direction quality values. The image information value being interpolated is determined in dependence on image information values assigned to pixels lying adjacent to the pixel being interpolated in the direction of interpolation. To ascertain a direction quality value for an image direction a pixel group having at least two pixels is selected; a single direction quality value for each pixel of the pixel group is determined, the single direction quality value being dependent on image information values assigned to image regions lying adjacent to the particular pixel of the group in the image direction; and a direction quality value is created as a function of the single direction quality values of the pixel group.

Abstract: The invention relates to a method and a circuit for carrier control in a quadrature demodulator, wherein a complex-value input signal (I, Q) is supplied to a mixer (1) to perform mixing with a mixing frequency (fm) to create a mixed signal (Ir, Qr), the mixed signal (Ir, Qr) is supplied to a processing section (s) to generate a processed signal (Ie, Qe), the processed signal (Ie, Qe) is supplied to phase measurement device (3) in order to measure a phase (?m) of the processed signal (Ie, Qe) and the measured phase (?m) is supplied to a phase controller (4) in order to control the mixing frequency (fm); wherein an idle time (z?d) is created at least during the processing in the processing section (2).

Abstract: A motion-compensated image signal interpolation unit (200) for generating an interpolated image being located at a first predetermined temporal distance (a) from the first image and being located at a second predetermined temporal distance (1?a) from the second image is disclosed.

Abstract: A method for converting video data in a first video format to video data in a second interlaced video format comprising: determining a number of frames of the first video format to map into a frame of the second video format, the frame of the second video format having four fields; determining a number of lines from each of the number of frames of the first video format to be mapped into each of the four fields of the frame of the second video format; selecting the determined number of lines from each of the number of frames of the first video format; determining a sequence for mapping the number of selected lines into the fields of the frame of the second video format; and mapping the selected lines from each of the number frames of the first video format into the four fields of the frame of the second video format according to the determined sequence.

Abstract: A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.

Abstract: An image processing unit for computing a sequence of output images on basis of a sequence of input images, comprises: a motion estimation unit for computing a motion vector field on basis of the input images; a quality measurement unit for computing a value of a quality measure for the motion vector field; an interpolation unit for computing the output images by means of interpolation of pixel values of the input images, on basis of the motion vector field; and control means to control the interpolation unit on basis of the quality measure. The quality measurement unit is arranged to compute the value of the quality measure on basis of a maximum difference between neighboring motion vectors. If the value of the quality measure is lower than a predetermined threshold, then a motion compensated interpolation is performed, else a non-motion compensated interpolation is performed.

Abstract: The invention relates to a method of decoding a video bitstream including base layer and enhancement layer coded video signals, the method comprising the steps of decoding the base layer and enhancement layer coded video signals to produce decoded base layer frames and decoded enhancement layer frames, and displaying the decoded base layer frames either alone or with the decoded enhancement layer frames. According to the invention, each poor quality frame of the base layer to be displayed is replaced by an frame obtained either by means of an interpolation between the two frames of the enhancement layer preceding and following the poor quality frame of the base layer or by only one of these two frames, for example the temporally closest one.