Abstract: Disclosed is a stereo signal processing apparatus, in particular for a digital BTSC television decoder, comprising a sub-channel signal processing section which comprises an input for inputting an input sub-channel signal, a DBX expanding means and an output for outputting an output sub-channel signal. The particularity of the present invention is that said sub-channel signal processing section further comprises a phase error compensating means for correcting a phase error of said DBX expanding means so that at said output of said sub-channel signal processing section the phase of the output sub-channel signal is essentially constant or zero over a predetermined frequency range.

Abstract: The invention relates to an apparatus and method for processing received data (I1/Q1, I2/Q2; d1, d2) of a radio interface, wherein the received data includes a sequence of data which have been transmitted for the purpose of error reduction through different branches of a carrier (Rk) of the radio interface, and which are combined into a sequence of data (DATAOUT) to be outputted, wherein the combining is implemented on the basis of carrier information values (Req,k, SINRk) of the different branches (k) relative to each other. A maximum ratio combining (MRC) is implemented in which the amplitudes of the branches of the carrier information (Req,1,(Req,2) are combined using a division method as a function of a disturbance information value (MIX, SINR1, SINR2) of the branches (k).

Abstract: A method of synchronizing a feedforward filter (46) that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols (60), wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method further includes the steps of estimating a channel impulse response from the plurality of samples, calculating a characteristic of the channel impulse response, and synchronizing (54) the feedforward filter in accordance with the estimated channel impulse response.

Abstract: The invention relates to a method for providing a motion parameter set and/or a picture repetition pattern from an input video signal, in particular for de-interlacing a video signal with using a candidate motion parameter set weighted with a picture repetition pattern value for calculating a motion compensated pixel from a pixel value of a first image. To provide motion compensation which accounts for field repetition patterns, minimizing an error criterion between at least one pixel value of a second image and at least the motion compensated pixel value by iterating the calculation of the motion compensated pixel with at least two candidate motion parameters sets and/or at least two picture repetition values, and putting out the candidate motion parameter set and/or the picture repetition value which provides the minimized error criterion is proposed.

Abstract: The invention relates to an arrangement for generating a 3D video signal, which produces a 3D effect when it is displayed on a screen, from an input video signal that is made up of frames, each of which has an odd field and an even field, where in order to generate the 3D video signal alternately an even field n and an odd field n?1 (or vice versa) and subsequently alternately an even field n+1 and an odd field n (or vice versa) are displayed, where in order to generate the 3D video signal a scan converter (4, 5) is used which can display two signals in the split screen mode, one of which is delayed by means of a special function memory (4) in the scan converter, where the non-delayed signal and the delayed signal are written, horizontally compressed by a factor of two, into a conversion memory (6) and, for the purposes of displaying on a screen, when they are read are scaled up by a factor of two in the horizontal direction.

Abstract: In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, television and/or video data, by means of at least one phase locked loop (40), wherein phase information is detected by means of at least one phase detector (44), in particular following the arrival of at least one rising edge and/or falling edge of at least one analog input signal (50; 50), at least one increment (24) is determined by means of at least one loop filter (30), to which the output signal (56) which is output by the phase detector (44) is fed, and at least one ramp oscillator (46) is fed the increment (24) which is output by the loop filter (30), such that inter alia the circuit arrangement (100; 102; 104; 106).

Abstract: The invention relates to a method for processing of a signal (s), wherein desired data (d(f(N))) are received via a desired channel (N) of a plurality of frequency channels (N?2, N?1, N, N+1, N+2) and unwanted data (d(f(N?2)), d(f(N?1)), d(f(N+1)), d(f(N+2))) can be received on a neighboring channel (N?2, N?1, N+1, N+2) and wherein the signal (s) is sampled with a sampling frequency (fa) to avoid aliasing of the desired channel (N) in order to create digital data (do), wherein the sampling frequency (fa=2f(N?1, N, N+1)) is set high enough for aliasing-free sampling of the desired channel (N) and at least one of the neighboring channels (N?1, N+1).

Abstract: The invention relates to an iterative method for determining an interpolated image information value in an image that comprises a number of image regions arranged in a matrix-like fashion having original image regions to which one image information value has been assigned, and having at least one image region to be interpolated. In order to determine an interpolated image information value, the method specifies a starting interpolation direction and determines a quality measure for the starting interpolation direction. At least one image direction is selected different from the starting interpolation direction and determining a quality measure for this at least one image direction.

Abstract: An audio input signal is filtered using an adaptive filter to generate a prediction output signal with reduced noise, wherein the filter is implemented using a plurality of coefficients to generate a plurality of prediction errors and to generate an error from the plurality of prediction errors, wherein the absolute values of the coefficients are continuously reduced by a plurality of reduction parameters.

Abstract: A method of synchronizing a feedforward filter that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols, wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method may further include the steps of estimating a channel impulse response from the plurality of samples, wherein the channel impulse response estimate is represented by a plurality of correlation values, identifying a maximum correlation value from the plurality of correlation values, defining a window relative to the maximum correlation value, calculating a characteristic of the correlation values within the window, and synchronizing the feedforward filter in accordance with the characteristic.

Abstract: The invention relates to an apparatus and method for processing received data (I1/Q1, I2/Q2; d1, d2) of a radio interface, wherein the received data includes a sequence of data which have been transmitted for the purpose of error reduction through different branches of a carrier (Rk) of the radio interface, and which are combined into a sequence of data (DATAOUT) to be outputted, wherein the combining is implemented on the basis of carrier information values (Req,k, SINRk) of the different branches (k) relative to each other. A maximum ratio combining (MRC) is implemented in which the amplitudes of the branches of the carrier information (Req,1, (Req,2) are combined using a division method as a function of a disturbance information value (MIX, SINR1, SINR2) of the branches (k).

Abstract: A method and system is provided for reducing mosquito noise in a digital image. The method and system receives an input luminance value for a first pixel in the digital image, and determines whether the first pixel is in relative close proximity to an object appearing in the digital image, based on a comparison of the variation between the input luminance value for the first pixel and luminance values of a first plurality of neighboring pixels. If the first pixel is in relative close proximity to an object, the method performs an average filtering of the input luminance value for the first pixel, based on the luminance values of a second plurality of neighboring pixels, to provide a filtered luminance value for the first pixel.

Abstract: In a device for processing baseband signal images (BS), a film detector determines whether a same baseband signal image includes both information from a film image and information from a video source image, information from one film image being present in at least two baseband signal images while information from one video source image is present in only one baseband signal image. A processing unit processing the baseband signal images in such a manner that in the presence of both information from the film image and information from the video source image in the same baseband signal image, for each film image only one of the at least two baseband signal images is used to obtain a display signal image (DS).

Abstract: Memory systems are disclosed which are comprised of a two or dual layer printed circuit board. Attached to the top layer of the dual layer printed circuit board are a memory chip and a memory controller with aligned, optimistic pin outs that optimized signal integrity layouts between certain high speed pins in a single layer. A set of high speed lines, including the data lines, that do not include any vias connect certain of the pins of the memory controller to certain of the pins of the memory chip. The high speed lines are covered by a sub-PCB that includes a copper lay that extends a ground or electrical plane above the top layer of the dual layer printed circuit board.

Abstract: The invention relates to a method of setting contrast in digital image processing in which a brightness distribution in the form of a histogram is produced from image pixels and the histogram is revised with the help of transfer functions, and in which a linear increase in contrast takes place in a region of the image.

Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to be stored in the data memory arrangement, and an address memory arrangement to store access addresses. The access addresses are logically linked to the given data type of the data, and/or a distribution of the data to the arithmetic/logic units is dependent on the access addresses, and/or a storage of the output data as the data is dependent on the access addresses.

Abstract: A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.

Abstract: Apparatus (40) comprising a plurality of output buffers (41.1-41.N) for driving the columns of an LCD panel (46). A bias generator (42) is employed for providing a common biasing current (Ibias) to all output buffers (41.1-41.N). Means (43) provide information regarding the physical position of a dot to be driven on the LCD panel (46) by counting the number of incoming load signals (LD). A switchable current source (42) changes the level of the biasing current (Ibias) according to the physical position.