Abstract: The invention relates to the field of signal processing, and particularly to method and apparatus for determining a peak power, a peak-to-average power ratio. The method for determining the peak power comprises: obtaining a sampling power at a current sampling time; comparing the sampling power at the current sampling time with an estimated peak power at the current sampling time; and when the sampling power at the current sampling time is greater than the estimated peak power at the current sampling time, determining the sampling power at the current sampling time as an actual peak power at the current sampling time. With the present invention, detection efficiency of the peak power is improved, and the peak power can be determined in real time at each sampling time.

Abstract: Disclosed in the present invention is a carrier communication method, device and system of low-voltage power lines, wherein, the carrier communication method includes: acquiring communication data comprising user data transmitted during communication and frame control data for assisting decoding of the user data; encoding the communication data using orthogonal space-time block codes and generating multipath transmission signals, in the case of unknown channel status; and transmitting the multipath transmission signals to an electric energy meter respectively via three-phase power lines. The present invention fully employs the characteristic of distinct inter-phase coupling of electrical signals at medium-and-high frequencies along power lines, and adopts various space-time encoding and decoding technologies, thereby improving the reliability of power line carrier communication between the concentrator and the electric energy meter.

Abstract: The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm aiming at reducing number of multipliers and adders. Compared with other FFT/IFFT design methodologies such as radix-4, it achieves the minimum multiplier use, the minimum adder use and the minimum operating memory use. On the other hand, the design architecture not only can support different FFT/IFFT size required by different VDSL2 profiles but also utilizing a novel pipeline control mechanism to reduce logic switching at low-speed profiles. This effectively further reduces the power consumption at lower profiles and enables our VDSL2 digital chipsets to compete with ADSL2+ systems in terms of power consumption.

Abstract: The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.

Abstract: The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.

Abstract: A novel method to divide the whole decoding process of the Viterbi decoder into four pipeline stages and the Viterbi decoder therefore. With an appropriate choice on the system clock, the invention trade-off the decoding speed with the hardware cost so that the designed Viterbi decoder is able to satisfy the decoding speed requirement for the highest speed profile in VDSL2 systems, 30 MHz profile. At the same time, with four-stage pipeline to just enough to meet the speed requirement, the hardware cost for the new designed Viterbi decoder is reduced compared with single-staged decoding.

Abstract: The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.