Patents Assigned to Trilogy Computer Development Partners, Ltd.
  • Patent number: 4772233
    Abstract: A low resistance connector includes a pin and mating socket. The socket includes a central bore sized for mating engagement with one end of the pin. The socket includes a number of longitudinal slots extending into and parallel with the central bore so the central bore is surrounded by a number of flexible fingers. Intimate electrical contact between the outer surface of the pin and the internal surface of the socket bounding the central bore is achieved by annealing the fingers of the socket to a dead soft condition and by the placement of resilient snap rings around the fingers to bias the fingers against the pin.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: September 20, 1988
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: David C. Hoffman
  • Patent number: 4737839
    Abstract: A semiconductor chip module with a flat mounting surface is disclosed. A wafer-scale silicon semiconductor chip is provided with electronic circuits formed therein. The chip has a metallized back face and contacts on the opposite, front face. A solder layer secures the metallized back face of the chip to the mounting surface substantially without voids.
    Type: Grant
    Filed: March 11, 1986
    Date of Patent: April 12, 1988
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: Roy J. Burt
  • Patent number: 4667220
    Abstract: A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: May 19, 1987
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: James C. K. Lee, Gene M. Amdahl, Carlton G. Amdahl, Richard L. Beck
  • Patent number: 4667219
    Abstract: A semiconductor chip module for a semiconductor chip having an exposed front face with a two dimensional array of contacts is disclosed. A connector plate is located proximate the front face of the chip. The connector plate has a plurality of apertures which correspond to and are aligned with the contacts of the semiconductor chip. A plurality of transmission elements are located proximate the connector plate opposite from the semiconductor chip. A plurality of flexible conductors extend through the respective apertures of the connector plate. The flexible conductors are electrically coupled to the contacts of the chip and to the transmission elements.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: May 19, 1987
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: James C. K. Lee, Gene M. Amdahl, Richard L. Beck, Robert F. Quinn, Jerzy R. Sochor
  • Patent number: 4658400
    Abstract: A test system including a data center, controller, interface, and device under test. The data center generates a test program which is applied to the device under test by the controller via the interface. The device under test includes circuitry structured for testing. The test system identifies the location of faulty elements on the device under test and stores these locations for use in a subsequent repair step.
    Type: Grant
    Filed: June 7, 1984
    Date of Patent: April 14, 1987
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: Harold E. Brown, Steven I. Mozsgai, Jason C. Chen
  • Patent number: 4628991
    Abstract: A testing chuck for providing a thermally controlled mounting for wafer scale integrated circuits includes a body having a flat upper surface, upon which the integrated circuit is mounted, cooled or heated by a fluid flowing through a number of channels formed in the body. The channels have entrance and exit ends fluidly connected to first entrance and exit plenums. Second entrance and exit plenums are connected to the first entrance and exit plenums by a number of entrance and exit distribution conduits. Fluid is pumped into the second entrance plenum, through the entrance distribution conduits, through the first entrance plenum and into the entrance ends of the channels. After passing through the channels, the fluid flows through the first exit plenum, exit distribution conduits and second exit plenum. The entrance and exit plenums are curved in the direction of fluid flow to reduce stagnant regions within the plenums to aid heat transfer and draining of the chuck.
    Type: Grant
    Filed: November 26, 1984
    Date of Patent: December 16, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: Wen-Ting Hsiao, Hubertus A. Everling
  • Patent number: 4617475
    Abstract: A wired voting circuit is described providing an output which follows the majority of input logic levels according to the equation: F=AB+AC+BC. A non-inverting signal voting node (D) and an inverting signal voting node (E) comprise a first and a second collector of an odd number of input differential transistor pairs (30, 32, 34) wherein said nodes are formed by wiring all of said first collectors together at one signal node and by wiring all of said second collectors together at the other signal node. Each signal node is coupled to a differential input of an output differential transistor pair (36). Currents are steered by the state of input logic onto either of the signal nodes, depending upon the input logic signal level. The signal level at each voting node is proportional to the number of input differential transistor pairs that steer current to the voting node. The voting scheme employs an odd number of logic inputs (T, U, V), such that an odd number of currents (I.sub.x, I.sub.y, I.sub.
    Type: Grant
    Filed: March 30, 1984
    Date of Patent: October 14, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: Robert M. Reinschmidt
  • Patent number: 4603345
    Abstract: A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic.
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: July 29, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: James C. K. Lee, Gene M. Amdahl, Carlton G. Amdahl, Robert J. Beall, Anthony Matouk, John W. Sliwa, Andrzej Kucharek
  • Patent number: 4597029
    Abstract: A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: June 24, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: Andrzej Kucharek, John Marshall, James C. K. Lee, Carlton G. Amdahl, Leo Yuan
  • Patent number: 4577398
    Abstract: A method of attaching a semiconductor chip to a mounting surface is disclosed. A solder barrier is applied to the mounting surface, and a preform of solder is located within the solder barrier. The preform is heated and then cooled in a vacuum to preflow the solder and secure the solder to the mounting surface substantially without voids. The semiconductor chip is then placed over the preflowed solder, which is reheated and then recooled in a vacuum to secure the chip to the mounting surface.
    Type: Grant
    Filed: September 7, 1984
    Date of Patent: March 25, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: John W. Sliwa, Roy J. Burt, Chune Lee, John MacKay, Cindy A. Johnson
  • Patent number: 4574470
    Abstract: A semiconductor chip module with a flat mounting surface is disclosed. A wafer-scale silicon semiconductor chip is provided with electronic circuits formed therein. The chip has a metallized back face and contacts on the opposite, front face. A solder layer secures the metallized back face of the chip to the mounting surface substantially without voids.
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: March 11, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: Roy J. Burt
  • Patent number: 4536122
    Abstract: A device for transferring semiconductor wafers from a first wafer carrier to a second wafer carrier with each wafer carrier having a pair of grooved sides for receiving and holding a number of vertically spaced wafers in horizontal planes and with each wafer carrier having front and rear openings. The device comprises a base having a flat upper surface. A wall member is secured to and extends upwardly from the surface midway between the sides thereof and near one end of the base. The wall member is spaced above the surface to present a slot for receiving a web forming a part of the wafer carrier as the wafer carrier moves over the surface. The wall member has a vertical end face which enters a wafer carrier as the wafer carrier is moved over the surface, whereby the wall member forces the wafers out of the first wafer carrier and into the second wafer carrier while the wafers remain in horizontal planes and vertically spaced with respect to each other.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: August 20, 1985
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: John M. Herrmann, Suzanne M. Voisin