Abstract: The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.