Abstract: A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.

Abstract: A 3D memory device comprises: a substrate; a plurality of U-shaped memory cells strings each including a first, bit line-side string portion or pillar, a second, source line-side string portion or pillar and a buried string portion formed in the substrate and connected to a first end of the first string portion and to a first end of the second string portion, the U-shaped memory cells strings including stacks of memory cells along the first and second string portions. Bit line selectors are arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines; source line selectors are arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines.

Abstract: A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.

Abstract: A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.

Abstract: A 3D memory device comprising: a substrate; at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line

Abstract: A 3D memory device comprising: a substrate; at least three first “U”-shaped strings of memory cells each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped string of memory cells including stacks of memory cells along the first source line selector string side portion and along the first bit line selector side string portion; and at least three second “U”-shaped strings of memory cells each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string porti

Abstract: A 3D memory device comprising: a substrate; at least one first group of at least three first U-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first U-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and at least one second group of at least three second U-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion.