Abstract: Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

Abstract: Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.