Abstract: A cascoded differential amplifier with a circuit for the injection of current to enhance the gain is described. The differential amplifier includes a differential pair of n-MOS FET's connected to a current source an a positive and a negative input terminal. A pair of isolation n-MOS FET's are inserted between the differential pair and a pair of current source loads. These isolate the current source loads from the differential pair. A current injector is connected to the drains of the n-MOS FET's of the differential pair. The isolation n-MOS FET's and the injected currents enhance the gain of the differential amplifier. A level translation circuit adjusts the output levels of the differential pair to levels required by circuitry attached to the output terminals of the level translation circuitry.

Abstract: A multiplexed analog-to-digital converter to accept multiple dissimilar analog input signals and convert each analog input signal to a digital code that represents the ratio of the magnitude of the analog input signal to the difference of an upper reference voltage source and a lower reference voltage source is disclosed. The upper reference voltage source is selected by an analog multiplexer from a set of voltage reference sources that include the power supply voltage source of the analog-to-digital converter for analog input signals that are reference to the power supply voltage source, and a precision reference voltage source that is referenced to the band-gap of silicon to provide an absolute measurement of the analog input signal. The lower reference voltage source is selected by a multiplexer from such references as a ground reference source.

Abstract: An operational amplifier with MOSFET's configured as capacitors provide frequency compensation over a large range of input frequencies is described. The operational amplifier has an differential amplifier stage with an inverting and an noninverting input. The difference of signals placed at the inverting and the noninverting inputs are amplified and place at the input of a folded cascode amplifier stage. The output of the folded cascode amplifier stage is the input to a linear amplifier stage. The output of the linear amplifier stage is connected to external loading circuitry. A first frequency compensation capacitor is connected between the output of the linear amplifier stage and a noninverted input of the folded cascode amplifier. A second frequency compensation capacitor is connected between the output of the linear amplifier stage and a virtual ground within the folded cascode amplifier stage.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: A circuit for turning off an indicator light operates in two phases that provide a first rapid discharge phase and a second slow discharge phase. This sequence dims the light in a visual approximation of the exponential dimming that occurs with lights that operate with power supplies that have capacitors that give a slow turn off. The preferred light is an electroluminescent element that will be called a glow-effect capacitor which stores sufficient charge for slow turn off. When a switch associated with the light is opened, an FET turns on to discharge the capacitor rapidly to a selected voltage. This FET is then turned off and other components discharge the capacitor slowly. The switching signal for this FET is formed as a logic function of the switch position (open or closed) and the occurrence of the selected voltage level on the glow-effect capacitor.

Abstract: A tablet system has an improved operation for saving power. During a digitizing period, the tablet supplies power to resistive sheets that produce analog pen position signals and to the sample and hold circuit and the analog to digital converter that operate on these signals. During a wait state, power is removed from these components and a separate circuit detects contact with the tablet surface by a pen. A pen activity circuit that uses less power is also disclosed. The pen activity detecting circuit has a resistor in circuit with the two resistive sheets. This resistor and associated circuits are independent of the normal path for signals that denote pen position and thereby allow these components to be turned off. When the pen is positioned on the tablet surface, the two resistive sheets are brought into contact in the normal way for detecting the pen position. During a period of pen inactivity, this contact produces a current in the resistor.

Abstract: A digital tablet of the type that multiplexes pen position signals has filtering and digitizing circuits arranged in separate channels for each of the signals that is to be multiplexed. The tablet pen is connected to receive an oscillator signal and the signal is picked up at each of the four corners of the tablet and applied to the corresponding channel. The separate channels permit the filters to be made sharper. The disclosure also includes improved circuits for processing the pen position signals.

Abstract: A new controller transfers data directly between the register of an I/O port and an ALU register in an operation that takes only one phase of a two-phase clock cycle. A transfer between an ALU register and main memory is also performed in one phase, and the entire transfer can be accomplished in one clock cycle. A connection is also provided between the ALU registers and the flag register, and when the incoming byte is a status byte, the controller can transfer the byte to the flag register where it can control the next instruction execution.

Abstract: In a digital to analog converter of the type having an array of current sources that are selected according to a digital input code to produce a current sum that is an analog of the digital code, current sources are arranged in pairs to form a dual current cell. When a dual current cell is selected, it produces two currents of differing magnitudes that are summed on two output busses with corresponding currents from other selected dual cells. These currents are subtracted to form an analog current. The two currents tend to have similar errors from a nominal current value and these errors are canceled by the subtraction. The two current sources of each dual current cell are oppositely switchable between two current levels, and the number of current sources is the minimum number commonly used for arrays of current cells having only one current source.