Patents Assigned to TRIVALE TECHNOLOGIES
  • Patent number: 12072585
    Abstract: This liquid crystal display device has a first substrate, a second substrate, a liquid crystal layer sandwiched between the first and second substrates, a seal, and a spacer. The seal includes: a first seal part having a linear shape in a first direction; a second seal part having a linear shape in a second direction; and a third seal part having a curved shape that smoothly connects the first seal part and the second seal part.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 27, 2024
    Assignee: TRIVALE TECHNOLOGIES, LLC
    Inventor: Hiroshi Umeda
  • Patent number: 12001104
    Abstract: This liquid crystal display device has a first substrate, a second substrate, a liquid crystal layer sandwiched between the first and second substrates, a seal, and a spacer. The seal includes: a first seal part having a linear shape in a first direction; a second seal part having a linear shape in a second direction; and a third seal part having a curved shape that smoothly connects the first seal part and the second seal part.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 4, 2024
    Assignee: TRIVALE TECHNOLOGIES, LLC
    Inventor: Hiroshi Umeda
  • Publication number: 20230258985
    Abstract: This liquid crystal display device has a first substrate, a second substrate, a liquid crystal layer sandwiched between the first and second substrates, a seal, and a spacer. The seal includes: a first seal part having a linear shape in a first direction; a second seal part having a linear shape in a second direction; and a third seal part having a curved shape that smoothly connects the first seal part and the second seal part.
    Type: Application
    Filed: June 30, 2021
    Publication date: August 17, 2023
    Applicant: TRIVALE TECHNOLOGIES, LLC
    Inventor: Hiroshi UMEDA
  • Patent number: 11231628
    Abstract: A display includes an antistatic circuit between a common wire and at least one of a signal wire and a scanning wire. The common wire is disposed in a non-display region, and receives a common potential. The signal and scanning wires are disposed in a display region. The antistatic circuit at least includes a first transistor having a floating control electrode, a first main electrode connected to the signal wire or the scanning wire, and a second main electrode connected to the common wire. The first transistor is provided in such a manner that a first capacitance between the control electrode and the signal wire or the scanning wire is larger than a second capacitance between the control electrode and the common wire.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 25, 2022
    Assignee: TRIVALE TECHNOLOGIES
    Inventors: Tatsuya Baba, Isao Nojiri